A simple fabrication process of vertical taper structures which can locally tune the thickness of silicon photonic devices.
Authors: Shunsuke Abe, Hideo Hara, Shin Masuda, and Hirohito Yamada.
This paper describes a simple fabrication process of verticaltaper structures which can locally tune the thickness of silicon photonic devices. For low-loss spot-size conversion, taper angles less than 10° are required. To fabricate the gradual-slope shape of the vertical tapers, we have developed a step-andexposure lithography process, which is realized by repeated light exposure to photoresist and movement of the wafer stage by using commercial steppers. The process is conducted at a lower temperature (~120°C) than the conventional process and is compatible with the CMOS process. Also, we have made a model of the lithography to predict the angle of the taper. Theoretical angles are consistent with the experimental results. We demonstrate the conversion of a 400-nm-thick silicon waveguide to 220 nm, whose length was 2.4 μm and insertion loss was measured to be less than 0.3 dB. The process enables to choose the optimal thickness for each silicon-photonic device.
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