FD-SOI Vs. FinFETs

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator (FD-SOI) with Philippe Magarshack, group vice president for technology R&D at STMicroelectronics; Marco Brambilla, director of engineering at Synapse Design; Mike Stuber, vice president of device engineering at Silanna; Wayne Dai, chairman and CEO of VeriSilicon; Naim Ben-Hamida, senior manager of mixed signal design and test at Ciena; Kelvin Low, senior director of foundry marketing at Samsung Semiconductor; Amir Bar-Niv, senior group director of design IP marketing at Cadence; and Mike McAweeney, senior director of product solution sales at Synopsys. What follows are excerpts of that conversation. To view part one, click here.

SE: What’s the verdict on working with FD-SOI versus bulk CMOS? Is it much different?

Ben-Hamida: We have used bulk from 90nm down to 28nm, so we have a good picture of what’s needed in that space. FD-SOI gave us another knob, which is biasing, for analog and high-speed performance. It allowed us to operate the core at a lower supply voltage level to enable the switching of the supply. That is a major gain. The method we are using is milliwatts per gigabit. In some market segments you need high density. You need multiple devices. Even though our power budget is not the same as it was, you have to deliver high performance, and 28 FD-SOI was the easiest way to do that.

Brambilla: It’s true that you get some additional flexibility on the physical implementation. You have an entirely new power grid that you didn’t have before, so you have to hook it up properly to make sure you don’t short anything. But at the same time, it allows us to relieve some of the complexity. You don’t need multiple CPUs. You can keep just one CPU because you can bias it to whatever frequency you want. That gives you one fewer power island to implement.

Low: That’s a big.LITTLE implementation?

Brambilla: Yes.

Low: So you use one CPU to run everything?

Brambilla: Yes. We use one CPU so we don’t have to do context switches. That saves memory. You save gates. And you save complexity.

SE: What’s different on the tools?

McAweeney: There are a few things different. Most of them are related to the body biasing. We started working with ST four years ago on a tool flow for 28nm FD-SOI. We built a system that gives you the RTL to GDS II flow with plug-ins that do design-rule checking and covers multiple corners. That’s a big challenge. That’s a lot more corners to cover because of the voltage range.

Bar-Niv: You’re starting with the porting process with the SOI. Is it different from any other processes? We’re doing a lot of analog design—analog IP. There are some porting challenges related to FD-SOI. Some cells need to be mounted differently than in bulk. Static timing analysis is a little more complicated than what we’ve seen in other processes because we don’t have advanced on-chip variation like we do in other processes. There isn’t a fixed number to give you that variation. But overall, it doesn’t add a lot to the porting process. There are no show-stoppers.

Low: There are a couple of wrong perceptions with FD-SOI. First, body biasing is not a new technique. People have been doing this at 45nm for a long time. Altera wrote a white paper about the key benefits of body biasing. There are techniques and tools for this. FD-SOI represents an extension of these tools and techniques from bulk. The second point involves comments about design disruptions in moving from bulk to FD-SOI. There are disruptions moving from planar bulk to finFETs, too. There are always some adjustments you need to do in moving from traditional devices to fully depleted, both in finFET and FD-SOI.

SE: How far will FD-SOI extend? Will it stay at 28nm or move down to 16/14, as well?

Magarshack: We have completed the next phase of 14nm FD-SOI and we are in the early phase of new design cycles. We have two cycles signed up and actively designing in 14nm FD-SOI as we speak.

Low: If you’re going to change your design techniques to body biasing or restrictions that come with other design techniques, will you be able to use that for the next node? We’re discussing that now to understand the impact.

SE: Is 14nm FD-SOI a 20nm process or 14nm process?

Magarshack: On the back-end of the line, it is the same as Samsung’s 14nm.

SE: So at 14nm, is that finFETs?

Low: It is planar. There is finFET on SOI, too, but that is different.

Dai: At some point, maybe 10nm, you will really see what’s possible. At that time, you will be able to tell whether a fin on SOI is better than a fin on bulk.

Magarshack: It’s too early to say. We have published research papers showing a 10nm finFET in FD-SOI. At this point we have not decided whether to turn this into a product.

SE: How far down does this extend?

Bar-Niv: The proof will support the process. We have talked about the different tools we are supporting for 28nm FD-SOI, 14nm FD-SOI and 14nm finFET FD-SOI. You can see we are looking at all of those nodes. For 28nm we have adopted the tools. We are working on 14nm FD-SOI, and 14nm finFET FD-SOI is the last one. The industry is looking at all of these flavors.

McAweeney: We’ve done a lot of work on 14nm, as well. We see no show-stoppers.

SE: Where does it end?

Stuber: That will be dictated by the process technology.

Low: Nothing is FD-SOI specific. This is litho-driven and cost-driven.

Magarshack: That’s why we have decided not to take on the burden of 10nm FD-SOI, because the back end of the line at 10nm is not only a nightmare for the process guys, with triple patterning and quadruple patterning. It’s also a nightmare for the design guys. Vendors are doing what they can to help, but with triple patterning and quadruple patterning you need to come up with four colors and pitching and more variability. There are companies that may need 10nm density, but that is more the exception than the general rule.

SE: Is FD-SOI a possibility for 2.5D and 3D?

Low: That will be independent of whether it is FD-SOI or bulk.

Magarshack: Because of the thermal capabilities, it will have an effect on 3D.

SE: What happens with biasing as you push into 2.5D and 3D? Does it still work, or do we need to use something different?

Magarshack: There is no implication. We can use it in 3D.

Low: As long as you consider it in the system-level design phase.

Dai: FD-SOI will be around a long time. It has an advantage for many applications and IP.

Low: Analog and RF don’t scale. But there is so much emphasis now on analog designs and they’re being left behind. It will be more important to go up, and for low power you may want to use 28nm.

Dai: You will never make money with analog at 10nm, and there are hundreds of companies in that field. Mixed signal people will feel much more comfortable working with FD-SOI. And we will go to two chips rather than one chip in a package.

SE: Did Ciena and Synapse consider 2.5D or 3D?

Ben-Hamida: 3D is still a possibility for us. We need to have that level of integration. Down the road, if we are talking about content that’s 30% analog and 70% digital, the amount of I/O and power to take information from analog and digital is inefficient.

Brambilla: SiP is already on the road map. The next step for us, for what we have to do, will be to port a radio into FD-SOI. Today there are Bluetooth solutions already integrated into digital. But we are discussing SiP.

SE: Is there any difference for tools in 2.5D/3D versus FD-SOI?

Ben-Hamida: It’s packaging technology. You can support any number of dies in a package, so it’s not directly related to the process.

Magarshack: I am not aware of any business case that will be a killer app. A lot of the consumer guys are considering 2.5D or 3D integration, but the cost of doing a through-silicon via is the equivalent of a 65nm 400mm-square die with elaborate TSV technology. So at the end of the day, the cost is much more expensive for system in package. The day there is an economical, viable product, a lot of the tools companies will be there with a solution.