A technical paper titled “Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits” was published by researchers at Imec.
“The introduction of highly scaled 2D-based circuits for high-performance logic applications in production is projected to be implemented after the Si-sheet-based CFET devices. Here, a view on the requirements needed for full wafer integration of aggressively scaled 2D-based logic circuits, the status of developments, and the definition of the gaps to be bridged is provided. Today, typical test vehicles for 2D devices are single-sheet devices fully integrated in a lab environment, but transfer to a more scaled device in a fab environment has been demonstrated,” states the paper.
Find the technical paper here. Published September 2022.
Schram, T., Sutar, S., Radu, I., Asselberghs, I., Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits. Adv. Mater. 2022, 2109796. https://doi.org/10.1002/adma.202109796.
Related Reading
New Materials Open Door To New Devices
2D materials add process challenges, but deliver significant performance benefits.Big Changes In Architectures, Transistors, Materials
Who’s doing what in next-gen chips, and when they expect to do it.
What’s Different About Next-Gen Transistors
Advanced etch holds key to nanosheet FETs; evolutionary path for future nodes.
The High Price Of Smaller Features
In a high-NA exposure stack, the resist is just the beginning.
Leave a Reply