High NA EUV Litho May Require Larger Photomask Size

By Jeff Chappell
With extreme ultraviolet lithography (EUV) potentially being used in pilot production in a few years, it raises the question of larger photomasks sizes—will the industry need them, and if so, when?

While there has been discussion of late about the possible need to transition to a larger mask size, veterans of the mask business may feel it’s déjà vu all over again. Back in the mid 1990s there was much discussion about transitioning from six-inch to nine-inch masks—so much so that standards were written. Then, as now, the transition (or more accurately, the lack of one) had to do with economics and the choice of lithography technologies used in semiconductor manufacturing.

The forthcoming choice today involves EUV, and as always when the discussion involves EUV, to answer these questions involves a combination of extrapolation and hypothesis. But the industry is finally getting close to putting EUV tools in fabs.

ASML suggested just last week that it is on track to deliver a throughput of 70 wafers per hour (wph) on its first production EUV lithography tool, the NXE:3300B, sometime next year. Ostensibly that will be with an 80 watt power supply, improving on the source in its current development tool, the NXE:3100, which currently can sustain 50 watts over long periods of time, according to the litho tool vendor.

If this holds true, the chip industry could see EUV exposure tools and pilot lines in chipmakers’ fabs within a few years’ time, although the throughput will have to continue to improve for it to move into mainstream production. The current consensus is that widespread use of EUV— assuming current estimates of power source improvements hold true—won’t happen until the end of the decade and beyond at the 10nm and 7nm nodes.

So in terms of the mask industry, it could be looking at a size transition around the 2018 to 2020 time frame. But worrying about that may be putting the cart before the horse, cautions Stefan Wurm, director of lithography for Sematech. “The industry needs to make the decision on doing high NA or not, and if it proves the right choice, it’s got to be a high NA solution that shares multiple nodes,” he said. While the question of high NA EUV is coupled with the need for a larger mask size, “it’s not something that will be decided tomorrow.”

Of more pressing concern is the availability of six-inch EUV photomasks in the 2015 time frame for those pilot lines, Wurm said. “The goal is very simple: make sure there is an adequate supply that supports the yield requirements for EUV ramp up.”

In fact, mask availability is of more concern than source power at this point, he said. Chipmakers are making a huge effort with regard to supporting lithography vendors on EUV source development to ensure success, he noted. Intel’s investment in ASML is a primary example.

“On the mask side it’s a little different because you have to look at the whole supply chain,” Wurm said. While suppliers are waiting to see the outcome of source development, it begs the question: Will they have time and resources to catch up once the source power is there? “We’re more concerned about the mask blanks supply chain than we’re concerned about the source,” he added.

There are still a number of technical issues to address if six-inch EUV masks are going to be ready for pilot production in a few years. “Everything that’s related to yield and masks and mask lifetime and blank defectivity is certainly at the center of that,” Wurm said.

Why larger photomasks?
Even with the adoption of EUV there aren’t necessarily economic or technical reasons for the industry to move to a larger mask size, or at least not right away. It depends largely on which way the industry goes to get to the resolution needed at the 10nm node and beyond, whether it adopts some sort of double patterning scheme with EUV or opts for a higher numerical aperture (NA) EUV exposure technology.

Increasing the NA—seen as necessary if the industry is going to avoid double pattering—will mean increasing the magnification of EUV exposure tools, which means a smaller exposure field size and consequently more exposures (and less throughput), unless a larger mask size is used.

Throughput, and thereby economics, is the key part of the equation. Based on the technical papers presented at SPIE and elsewhere in recent years, it appear the techniques used to achieve the higher NA would cut throughput by as much as 50%. This can be alleviated somewhat with a larger mask size, noted Franklin Kalk, CTO of Toppan Photomasks.

“It’s interesting because the mask size can help the throughput, but it doesn’t bring it back to where it was,” he said.

Furthermore, it all comes back to EUV source power as well. “If we increase the mask size, it won’t improve the throughput without the (EUV source) power,” said Banqui Wu, Applied Materials’ CTO for its photomask etch products business. “People assume we have the power. If we get the power, we can improve both the resolution and the throughput.”

But what about bigger wafers, too?
As Kalk and Wu suggest, if the source power doesn’t continue to scale as hoped, even if EUV is put into production there would be little need for a larger mask size because high NA EUV wouldn’t be feasible without the requisite source power. But, as Sematech’s Wurm notes, if the source power isn’t available for high NA EUV at the end of the decade, it probably will mean that EUV never made it into production in the first place, and thus it will become a moot point.

Even if high NA EUV proves viable, the smaller exposure field possibly could prove beneficial with high NA EUV at the 10nm and 7nm node, in spite of the extra steps and lower throughput that would result. Yield and defect control conceivably would be easier to manage with the smaller exposure field, Wu noted.

Wrapped up in the argument for larger mask sizes is the transition from 300mm wafers to 450mm wafers, although the wafer size transition wouldn’t necessarily require larger mask sizes, just as the migration from 200mm to 300mm wafers did not. “If the industry doesn’t adopt EUV for production, or it is used on a very limited basis, it seems unlikely the industry would opt to migrate to a larger mask size,” Kalk said. “In principal, on 450mm (wafers), it doesn’t really require a larger mask.”

Applied’s Wu said that a larger mask size in combination with 450mm wafers could provide benefits in terms of wafer etch and chemical-mechanical planarization (CMP). However in terms of throughput, in and of itself a larger mask size wouldn’t really result in any improvements without the adoption of EUV, regardless of wafer size, he said.

Bigger mask size means bigger—much bigger—CapEx
So if high NA EUV is ready for the 10nm node, a transition to a larger mask size, likely nine-inch masks, seems likely. Will the industry be ready? That will remain to be seen, but one thing everyone can agree on: It will require considerable capital investment cycle.

“We’re always used to scaling equipment; we’ve been doing it since the three-inch (mask) days,” said Amitabh Sabharwal, general manager for photomask etch products at Applied. “If there is significant pull and there is an industry demand, we can do it.”

But a transition won’t be cheap.

“The bottom line is it’s going to cost a lot of money to do it,” said Toppan’s Kalk. “We haven’t done a thorough analysis of a nine-inch EUV mask (manufacturing) line or 12-inch EUV capable mask line, but it has to be approximately 200 million,” he said – roughly half the cost of a leading edge manufacturing line today producing photomasks for 28nm manufacturing.

It could mean changes in the photomask supply chain as well. While the big three semiconductor photomask suppliers—Toppan, Photronics and Dai Nippon—have kept their hands in the leading edge by partnering with large IDMs, the pool of those playing at the leading edge dwindles with each technology node. With only a handful of companies likely to be developing chips at the 10nm node, and the considerable capital expense involved, further consolidation among merchant mask suppliers could be in the offing in the years ahead.

Furthermore, with only a small number of chipmakers producing chips at the 10nm node there may not be enough tools sold to justify having two or more suppliers for each piece of equipment. For example, “we’re not going to find multiple providers of writers or etchers,” Kalk said. “I just don’t think that’s going to happen.”

Aside from the economic issues, there will be many technical issues to address when it comes to migrating to a larger mask size along with EUV, such as critical dimension (CD) resolution and mask metrology and defectivity. This is not to mention the technical hurdles that still exist for six-inch EUV masks.

There also is the question of using nine-inch mask sets with six-inch mask sets. While at first glance it may seem plausible to continue to use six-inch mask sets for non-critical layers even as nine-inch masks are used for critical layers, thereby saving costs, this method would introduce its own technical hurdles, such as alignment.

EUV mask availability—be it six-inch or later nine-inch masks—is perhaps indicative of a larger phenomenon in the chip industry beyond EUV and photomasks. “The health of the supply chain in general, not just on the mask side, will need more attention in the industry,” said Wurm. The costs for equipment and materials vendors continues to increase, and their capability to support R&D doesn’t always keep track with what the industry requires of them.

“That’s something the industry needs to keep in mind,” he said. “How can we work together to make sure we have a healthy supply chain in all areas?”