How Hard Is FD-SOI Design?

Fully-depleted silicon-on-insulator (FD-SOI) manufacturing technology reached of point of readiness for mass production at the end of March. Along with that, it’s now clear that while there are some impacts on the design flow, those impacts are not game changers.

For one thing, the tools required are the same ones currently used for 28nm planar bulk CMOS. The only difference is there are some technology attributes that need to be characterized.

“FD-SOI is what we call a wide-ranging technology meaning it can span the lowest leakage possible, and also highest performance possible through the use of body bias,” said Kelvin Low, senior director of foundry marketing at Samsung. “Because of body biasing, the designer can have the option to push performance. Then with reverse body bias that is introduced into the circuit, the designers can have the lowest leakage flow for the design. So the ability to integrate body bias into the design flow will be the new element.”

To do this, designers will have to deal with additional process, voltage, temperature (PVT) points because the reverse body biasing comes with its own respective PVT points. As such, the number of characterization points will increase because it means there are more options to use for a design, Low explained.

Now, the important challenge is to make sure the PVTs are available, which means the IP provider and foundry must team up to generate these PVT points.

Cadence has been working with STMicroelectronics for some time and had a production toolset in 2011 to support ST’s 28nm FD-SOI. Vassilios Gerousis, a Cadence distinguished engineer, explained the main changes came on the physical design side, namely how to connect the back bias to tap wells and connect them to the standard cells and to other IP.

“The main methodology is how to connect those and also, if you deal with them in terms of discrete points, then it fits into what we call multicorner methodology for timing,” Gerousis said. “You can use multicorner methodology if you have a discrete point.”

He noted that some design engineers wanted to use continuous points, which is very hard to support. “We don’t use SPICE, at least on the digital side. We have STA, which does require discrete points of timing models. To do it, any value of the back bias or VDD requires a lot of changes to the toolset. As a result, discrete points are much better. That means people need to characterize more libraries for it, but that’s what a lot of people do anyway for regular CMOS — multiple corners of the CMOS timing model. Essentially, the flow is similar. The only difference is how you do the bias connection.”

In the digital design tool realm, Gerousis explained that some changes had to be made to deal with low power. “The more you drive low power, the better it fits into the FD-SOI story. Essentially what you need to do with FD-SOI is (DVFS), and that’s the support that is needed for people to use it if you want to use the full capability of FD-SOI.”

Michael White, director of product marketing for Calibre Physical Verification Products at Mentor Graphics, agreed that from the design side, it’s not as big an impact as might be imagined.

When it comes to FD-SOI and physical verification, including DFM, fill, circuit verification perspective — it really looks like another PDK, another set of decks, he said. “Those decks are really not that different from a traditional CMOS. The front end is going to be slightly different. You’re going to have different models so the parasitic extraction and SPICE is going to be unique, but the rest of your process as far as how you’re running the tools, how you’re debugging your design, doesn’t really feel that different.”

He also noted that one big concern has been whether there will be access available to the IP from suppliers supporting an FD-SOI process to allow design teams to build chips. “I heard lots of angst at least a couple of years ago about that. My perception is that’s improving and I’m sure Samsung is trying to make sure they’ve got a competitive IP offering in place to make FD-SOI interesting. There is certainly lots of discussion about making sure that it is available.”

Along these lines, another concern is whether there will be access to existing third party IP that can be integrated into a design targeted at FD-SOI, White said. “How do I have to re-factor the IP that I made for maybe some previous sister design on bulk CMOS? How am I going to have to re-factor that to now work with FD-SOI.”

In addition to issues around IP, there will be some optimized extraction required to address RF-SOI processes, which will be discussed during an upcoming session in Mentor Graphics’ booth at DAC.

The differences between bulk CMOS 28nm and FD-SOI are much smaller than 28nm bulk CMOS to 20 or 16 or 14nm bulk CMOS. “So if I’m a company super interested in low power, maybe not necessarily needing to do the jump to 16 or 14, the level of effort for me to get better power out of FD-SOI is going to be quite a bit smaller than jumping to 16 or 14. The number of design rules, the complexity of the design rules, making that lateral jump, is basically the same order of magnitude. You’re not having significantly more complex DRC and so on. Making that jump from 28 to 16/14 [in CMOS], you’re looking at on the order of 25% to 30% more design rules, 25% to 30% more operations for each design rule. There are more design rules, they are much more complex design rules, and you’re now jumping into the world where you need to start designing and dealing with . Many, many companies have now been successful in doing so, but it takes work. It takes resources to think about it. You need training from people who understand the world of double patterning, so there’s an energy barrier. You need to spend resources and money to be successful at 16 or 14, and less to do this lateral jump from 28 bulk to 28 FD-SOI.”

The tools are there, the third party IP is coming along, and the manufacturing technology is ramping. While Samsung is only willing to talk about a couple of designs for FD-SOI being taped out by STMicroelectronics, it’s only a matter of time before other design teams from Freescale, Synapse Design, VeriSilicon — which all have publicly stated their support for the technology — also have stories from the trenches to share.