Companies are selecting preferred flows, but the process details are changing rapidly to meet the needs of different applications.
Hybrid bonding is gaining traction in advanced packaging because it offers the shortest vertical connection between dies of similar or different functionalities, as well as better thermal, electrical and reliability results.
Advantages include interconnect scaling to submicron pitches, high bandwidth, enhanced power efficiency, and better scaling relative to solder ball connections. But while some chipmakers do have hybrid bonding in high-volume manufacturing (HVM), the cost of the process is too high at present for mass adoption. And because hybrid bonding pulls together front-end and back-end lines, assembly processes such as die placement now must meet front-end specifications.
Other challenges include the need for better copper dishing uniformity, faster die-to-wafer placement with superior alignment, multiple bonding and de-bonding carriers that drive up cost, and lower temperature annealing capability. Finally, particle levels must be driven down especially during die placement and dicing steps.
“Successfully scaling hybrid bonding into high-volume manufacturing requires addressing challenges related to defect control, alignment precision, thermal management, wafer warpage, material compatibility, and process throughput,” said Alice Guerrero, principal applications engineer at Brewer Science.
AI chiplets and modules are a huge driver for hybrid bonding and advanced packaging. Their high performance and high price tag help fuel the industry. In fact, DRAM makers are evaluating the net gain of moving from solder-bump bonding (by thermocompression) to hybrid bonding (see figure 1). The next generation scaling after hybrid bonding is sequential 3D integration, where bonding extends to even thin films.
Hybrid bonding is a pivotal enabler for the larger goal of breaking up SoCs into individual technology blocks called chiplets. “Today we have a kind of disaggregation of a monolithic IC, where you will have specialized technologies such as logic and SRAM memory for SoCs, logic, and I/O devices,” said Eric Beyne, senior fellow, vice president for R&D, and program director for 3D system integration at imec. “We need to drive to a seemingly monolithic or a fully integrated solution, where you don’t see the boundaries between the different devices. We have to break this barrier that going off-chip creates a penalty in terms of bandwidth or energy usage.”
High bandwidth memory (HBM) makers could move to hybrid bonding or fusion bonding (dielectric-to-dielectric), but there are drawbacks. “Fusion bonding is really a proven manufacturing process right now for 300mm wafers, and that bonding works very well for HBM,” said Thomas Uhrmann, business development director at EV Group (EVG). “HBM is currently stacking 12 chips, and the manufacturers will soon go to 16 layers. But because the performance is not the same for every chip, it’s basically the weakest link that limits the performance of the whole stack. It’s not so much a question of yield, because the DRAM wafers are yielding very well. Speed binning is actually a big hurdle. You need to implement pre-sorting in order to compensate.”
Strong drivers
The wafer-to-wafer bonding scheme was the first technology out of the gate for hybrid bonding of CMOS image sensors, where a pixel array chip is bonded to a logic chip to maximize the area for backside illumination. Now, other applications are catching on, combining processor/cache, 3D NAND, microLEDs, as well as AI modules for LLM applications like ChatGPT.
The concept of chiplet integration in advanced packages offers a new level of flexibility. “In advanced packaging you can customize the system,” said Jon Herlocker, CEO of Tignis. “You can say, ‘This piece of the logic is super complex, and so I’m going to go do that at an advanced node in a 300mm foundry, but I’m going to take the other functions from one or more more mature nodes and place it on the same package.’ You can effectively take advantage of mature nodes with their predictable, high yielding processes, and therefore lower the overall risk. So once you’ve committed to doing advanced packaging — and there is a certain risk in advanced packaging — then there’s all sorts of benefits for pulling as much stuff as you can out of your complex chip and using more mature technologies, then connecting it via that advanced package.”
Power management and the need for power efficiency are additional drivers for chip stacking and new bonding methods. Hybrid bonding enables companies to create a “path of least resistance,” which means shorter interconnects, greater interconnect density, as well as greater heat removal challenges.
Within this evolution is the need to reduce power consumed by semiconductors. Scalability becomes critical (see figure 2). “We have power walls, so typically energy density today will be 100 watts per square centimeter but in the future we’ll need to evacuate at 500 watts per square centimeter, so quite a significant increase,” said Beyne. “So that is one of the problems but perhaps not the most important problem. If we’re talking about 500W per square centimeter at such low voltages, that means 500A per square centimeter so you need very big copper cables to do so. So sending it through the microbumps and the solder bumps may not be the best approach. How do we solve that? We can integrate the power management system much close to your device. And possibly we don’t just send 1.7V through the full stack but maybe you will come up at even a higher voltage of 48V, for instance, and then use DC/DC conversion at the package or board level to reach the final voltage.”
Fig. 1: Fine-pitch hybrid bonding, even with backside power distribution, leads to high heat concentration that requires improved heat sinks. Source: imec
In addition to power distribution, Uhrmann noted that testing with hybrid bonding adds another layer of complexity. “Whereas bumped devices can be readily tested, with hybrid bonding it’s not that easy. You could create a double layer for the hybrid bond, because then you have an underlying layer that you can test, but you still need to have the bonding layer on top.”
How the process works
The wafer-to-wafer bonding process is more mature than the die-to-wafer schemes, but it has a major disadvantage — dies must be identical in size. This has worked out well for applications like SRAM on processor stacks, but much greater flexibility in design and manufacturing requires die-to-wafer bonding, where a smaller die is bonded to a larger die. Here, the concept of collective D2W bonding is becoming attractive (see figure 2).
Fig. 2: Collective die to wafer hybrid bonding flow adds an acoustic layer (grey) to the laser release layer (green) to bring transfer yield up to 100%. Source: imec
As shown, the process uses multiple carriers, including silicon and glass. The process flow for hybrid bonding takes wafers that have been processed through the final metallization layer, then performs steps similar to on-chip damascene processes. The dielectric etch optimally forms square cavities in the SiCN dielectric, which then are filled with barrier metal, copper seed, and copper fill by electrochemical deposition (ECD). The CMP process that follows is optimized for extremely high across-wafer uniformity to produce as smooth a dielectric surface as possible with a simultaneous small recess in the copper pad areas.
Step two involves mounting the wafer to a carrier, and then grinding/thinning of the silicon wafer. The wafer is flipped and bonded to a second carrier, and a photoresist layer is spun on to protect the surface during dicing on a tape frame. A third carrier bonds to this die field, and the photoresist is stripped. Placement on a new carrier prepares it to bond with the target wafer, followed by de-bonding by blade, IR laser, or UV light.
Next, a dielectric activation step in a vacuum chamber uses a plasma to optimize the bonding surface with dangling Si-O– bonds. This is followed by a DI water rinse to hydrate the dielectric. Face-to-face (or face-to-back) bonding of the second wafer, processed up through copper CMP in the same manner as wafer 1, is then aligned with and bonded to wafer 1. Then the wafer pair goes through furnace annealing at 350°C for two hours.
Now the bonded pair may be thinned for the next wafer. Imec and others have shown that very thin (50 µm) to very thick die (775µm) can be transferred from a temporary carrier to a target wafer with transfer yield and bond yield of 100%. For ultra-thin die, silicon carriers are preferred. Glass carriers do allow UV de-bonding, but they are not compatible with front-end tools.
Imec, Brewer Science, and Suss MicroTec recently demonstrated that collective die-to-wafer bonding flows can be extended to three and four wafers. [1] A so-called acoustic layer was added to the organic laser release layer to absorb the shock wave induced by the ablation (de-bond) process, which can damage die edges. Notably, the alignment, measured by IR microscopy, is a function of the flip-chip tool and the bonding tool alignment combined.
Transfer yield and bond yield are critical metrics that reach can 100% with fully optimized fab and assembly processes. Extending collective die-to-wafer flows to two, three, and four wafers complicates the process due to warping, incomplete adhesive removal, and possible die damage during processing. [1]
The carrier substrate is selected based on the temporary bonding material (TBM) and its de-bonding capability. “The ability of an adhesive to temporarily bond a die to a TBM is governed by a combination of its mechanical, thermal, and chemical properties, as well as the condition of the die surface,” said Brewer Science’s Guerrero. “Generally, the interplay between bond head temperature and carrier (chuck) temperature will be tuned for optimal die adhesion based on the thermal properties of the TBM. Laser de-bonding is best for minimal force during die release.”
Guerrero noted there are risks for die damage of thin dies, but these risks can be mitigated through material and process design. “Mechanical de-bonding is a more cost-effective solution due to equipment costs relative to laser but is not as universal in its application fit,” she said. “UV release is not widely available, and is challenging to implement at a carrier level. UV release tapes are readily available and are the most economical de-bonding approach, but it will have limitations with handling dies less than 50 µm.
Tool cleanliness is paramount to prevent voids at the bond interface, which show up as white dots on a black background on C-SAM maps. “What’s interesting is that some particles will still move on the surface because of the way that you’re cleaning and the process that you’re doing. So it doesn’t mean that you can’t have one particle,” said Laura Mirkarimi, senior vice president — head of SEMI Engineering at Adeia. “It is a process that can handle some particles, but large particles that don’t move can stop it from bonding. That bond front moves so fast in the wafer bonding, and even in the die-to-wafer bonding, so it’s really a spontaneous bond that needs to be managed through careful treatment of your surfaces.”
This explains why multiple cleaning steps must be optimized throughout the hybrid bonding flow.
There are other recent process improvements including:
The latter process on silicon carriers also allows for silicon carrier reuse, which reduces the number of process steps and lowers cost of ownership. “We’re using a completely different kind of release layer, an inorganic that is front-end compatible,” said EVG’s Uhrmann. “But the silicon carrier can be used all over. So you now can have carriers that work with fusion bond, where you can also carry around hybrid bonded wafers or very thin devices, even epi layers. So it expands the whole portfolio toward front-end transfer, but it’s not limited to that. And high accuracy means far less than 100nm.”
Such developments also can affect sustainability. “There’s a lot of cost behind water recycling and keeping the water clean,” he said. “With grinding and polishing, you are generating a whole lot of particles — even nanoparticles — so the filtering is expensive.”
While there is much talk about face-to-face bonding, many processes need face-to-back bonding, which means you first need to put it on the carrier and thin it down, and then transfer it to another carrier,” he said. “So you have the thin device wafer, and then if another carrier wafer needs to be thinned, you sacrifice two wafers, which is not cost-effective.”
Until recently, the HVM-capable flip-chip bonders had alignment tolerances of ±3µm (3 sigma), but that has been driven down to 1µm (3 sigma). “A rule of thumb for alignment accuracy is that the bonder must be 0.1 to 0.25X the pad diameter, or 100 to 250nm for a 1µm pad,” said Adeia’s Mirkarimi. And bonders with submicron accuracy recently have been developed and made available from multiple vendors, including BESI (BE Semiconductor) and Suss MicroTec.
“Despite its advantages, D2W HB has two assembly challenges,” said Feras Eid and colleagues at Intel. [3] “The first is alignment, with current and even next-generation bonding equipment being unable to meet the placement requirements of sub-1µm pitch. The second is throughput, with the D2W HB attach step being the slowest and most expensive step in the full HB flow, even at today’s relatively relaxed pitches (e.g., 9µm).”
As a result, Intel and others are exploring alternatives to pick-and-place, such as fluidic self-alignment that uses tiny beads of water and a guiding patterns on both dies to self-align structures. [3] The process is being jointly developed by CEA-Leti and Intel. Importantly, die-to-wafer can be misaligned in x, z and theta (rotational) directions. Liquid confinement brings down the die-to-wafer misalignment to 200nm under specific conditions. While not suited for production yet, the process has the potential to replace time-consuming die placement with an estimated 10X improvement in throughput.
Although the semiconductor industry has proven hybrid bonding for certain applications, there is a continuous move toward reducing the number of wafer steps and cost. While the companies making AI chips can afford more complex processes, for the technology to penetrate less expensive systems it must be simpler.
Direct die-to-wafer bonding processes are significantly less complex than a collective die-to-wafer approach that places only known good die on a reconstructed wafer, which is then bonded to another wafer. However, direct bonding suffers from contamination issues because the die placement tool directly contacts the sensitive bond surface, requiring very high tool cleanliness and perhaps in situ die cleaning capability.
Thermal challenges
The new level of power density from hybrid bonding necessitates new approaches to relieve the heat. Imec researchers developed microfluidic cooling technology using 3D printing technology. With that approach, the diameter of the channels is important.
“At 100 to 300 microns you have more native ability for the water to flow into the structure, generating water jets that go directly to the back of the die and cooling the system directly like a showerhead.” Beyne said. He noted that by additionally modifying the backsides of the die with an interlacing pin-fin structure, heat transport is improved further, achieving heat transfer coefficient values like 10W/m2-K. “Overall, the cooling could reduce die temperature by around 50°C.”
Each time a hybrid bonding process is scaled to a smaller linewidth and pitch, bond strength and alignment must improve. Bond strength needs to be even better, as does the flatness of the wafer, which is largely dictated by fab’s chemical mechanical polishing (CMP) capability.
In manufacturing, solder bumps are at the 45µm pitch level. “Wafer-to-wafer bonding provides a path to 400nm and toward a 200nm pitch, but the die-to-wafer is a bit behind them, in the 10 to 1µm range, which probably is the sweet spot for that technology,” said Beyne.
Conclusion
Device makers, equipment companies and materials suppliers are collaborating on multiple approaches to find process flows that yield the best performance at lower cost so that non-leading-edge devices can take advantage of all that hybrid bonding has to offer. But the new technology is undergoing growing pains. It requires new procedures, new tooling capability and even some new processes.
In addition, different applications have different needs, so it is likely that several approaches will emerge as leaders. For the time being, though, hybrid bonding processes and the supply chain are very much in flux, which is not uncommon with new technologies.
References
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