Low-Power IC Design Without Compromise

In the process of creating ICs, the digital implementation stage is focused on meeting the performance, power, and area (PPA) targets defined for the design. Traditionally, when talking about PPA metrics, “performance” has been the primary focus, with power and area recovered where possible, after meeting timing.

But as designs have moved to smaller, more advanced process nodes, and as switching activity has become a dominant component in power consumption, power has at times pushed “performance” aside to become the dominant focus in PPA. Of course, designers want lower power, but not at the cost of slower-performing chips.

Digital design software helps SoC designers achieve their design targets but can’t always achieve the lowest power without sacrificing performance and, many times, time to market. A modern, flexible IC digital implementation tool changes the equation so that designing for best power inherently delivers better results all around.

Here’s how a newer place-and-route software with a single-unified data model, innovative low-power methodology, and intrinsic intelligence helps designers quickly converge on low-power-optimized performance, power, and area (PPA).

Low power technologies in digital implementation software

How can strict power specs be achieved without sacrificing performance during the implementation phase of the IC design process? It depends on how well the software handles multiple power domains and the kind of optimizations it performs throughout the flow to achieve low power goals. Physical design software can address these power challenges in several ways, but this blog will focus on a couple of elements of a unique technology in the Aprisa digital implementation tool from Siemens called PowerFirst.

• PowerFirst optimization starts from best power and then optimizes to achieve the timing target
• PowerFirst CTS considers both power and timing cost during clock tree synthesis

PowerFirst works because Aprisa is built on a detail-route-centric architecture with a unified data model that is shared throughout the entire flow, allowing real routing information and parasitics to be available at each step in the flow.

Aprisa’s PowerFirst optimization takes “best power” as the top priority and works towards that goal throughout the flow, using activity-based placement and routing for lower dynamic power. By starting with the power metric as the top goal during optimization, designers can achieve the best possible power for that node, library, and design specs, and then optimize from that point to reach the timing target. This method is more effective than trying to recover power once the most power-hungry cells have already been used in the design to achieve timing. This methodology also considerably helps to save area.

However, designing for power is not just a matter of choosing cells that save power. That’s why PowerFirst is considered a methodology, not a single feature; it touches all engines and steps in the flow to ensure power-centric design implementation that can ultimately meet the performance targets for the chip.

Results from a customer’s 7nm low power design demonstrate the effectiveness of the PowerFirst methodology, as shown in table 1.

Activity-driven methodology reduces dynamic power

Aprisa’s core engines have access to the available switching activity through a common data model, which it uses throughout the flow to optimize dynamic power.

During placement, Aprisa ensures that high-activity nets are shorter to reduce capacitance compared to the low-activity nets which can handle longer wires (figure 1). During clock tree synthesis (CTS), the net connections of high-activity flip-flop clusters are kept short to reduce capacitance, and the low-activity nets can be spread out to relieve congestion. At routing, the tool increases the spacing on the high activity nets to reduce coupling capacitance, while low activity nets take advantage of using the available routing tracks more efficiently.

Optimizing for low power from the start gives better results than using power recovery techniques later in the flow when the design is congested; the routing tracks are no longer available and making any changes produces endless timing ECOs.

Fig. 1: Managing coupling capacitance at various steps.

Clock transition fixing for better power

Aprisa’s power-aware CTS can reduce switching power by slowing down the sharp transition of the buffers on the clock tree without causing transition violations. This technique achieves significantly lower switching power for both cells and nets, and in the process can also save area.

Trade off small timing for large power reduction in CTS

When building the clock tree, the goal is to achieve the best latency and skew, but this can result in using larger buffers or too many buffers (figure 2).

Fig. 2: Trade off small timing for large power reduction in CTS.

With a very tight skew, the launch and capture clocks are balanced and the datapath can more easily meet timing. With a larger skew, the datapath may not initially meet timing, but it can be fixed through optimizations like upsizing a cell or adding a buffer. Allowing a larger skew ends up relieving the costs in terms of power that come with a very tight skew, even on the critical branch.

For the non-critical branch, large and smaller buffers are sometimes used in combination to achieve a tight skew. But if the path is not critical, the timing is already met, and the tighter skew is not needed. This means that a little timing can be sacrificed to reclaim other metrics like power by switching some of the large buffers for smaller ones.

Conclusion

It’s possible to reduce power during place-and-route, and also to achieve optimal PPA by using a modern software designed to do so. Aprisa is built on a detail-route-centric architecture that uses real routing information and parasitics in every step in the flow, resulting in better overall PPA, consistent timing and DRC, and excellent correlation to signoff tools.