Managing Yield With EUV Lithography And Stochastics

Identifying issues that actually affect yield is becoming more critical and more difficult at advanced nodes, but there is progress.

Although they are closely related, yield management and process control are not the same. Yield management seeks to maximize the number of functioning devices at the end of the line. Process control focuses on keeping each individual device layer within its design specifications.

In lithography, for instance, process control seeks to transfer the mask pattern to the wafer as accurately as possible. Accuracy is defined by such metrics as critical dimension (CD), roughness, and placement error. Potential defects include bridges, breaks in line and space patterns, and filled or merged holes in contact and via patterns. Deviations from the intended pattern can be random or systematic in nature.

Finding the defects that matter
Not all resist defects are printable, though, and not all feature variability leads to device failures. In work presented at this year’s SPIE Advanced Lithography and Patterning conference, KLA’s Franz Zach explained that yield-focused process models must know exactly what part of the intended circuit is failing, why, and how often. The error budget considers how many instances of a challenging feature exist and defines an acceptable number of failures.^⁠[1]

In particular, Zach said, yield loss is driven by the tails of the process distribution. “If the center of the distribution doesn’t have good yield, you don’t have a manufacturable process.” For that reason, standard deviation alone does not provide enough information. Defect mechanisms with strong tails will dominate overall yield. The yield management team needs to know what those defect mechanisms are, from which it develops a mechanism-specific metrology and inspection plan. For example, the occurrence of resist bridge defects may be entirely random, but drift in the etch process might make those defects more or less likely to print. The etch process, then, is where yield management efforts will have the greatest impact.

As process complexity increases, the amount of information about the wafer captured by any single metrology step decreases. A single measurement might be adequate to characterize the process, but not correlate with overall yield. On the other hand, considerable time will pass between a wafer start and the first electrical measurements from that wafer. Engineers depend on metrology to identify potentially defective wafers quickly, without waiting for electrical measurements. Neural network analysis can offer valuable insight because it considers all available data, rather than starting from assumptions about which measurements are important.

Shay Yogev and colleagues at Applied Materials and imec used a convolutional neural network (CNN) to predict device threshold voltage, measured at the end of the line, from e-beam images collected at five different points — after STI formation, after gate etch, after dummy gate removal, after contact CMP, and after metal 1 etch.[2] They found that material variation was more strongly correlated with threshold voltage than geometrical variation. Specifically, the CNN identified a tungsten deposition signature in the post-CMP images, leading to a step change in the predicted threshold voltage. While STI/gate overlay measurements had the strongest geometrical correlation with threshold voltage, they did not predict the ultimate test results. Rather than relying solely on either post-CMP or post-gate measurements, though, accumulating information layer-by-layer increased the accuracy of the overall prediction. In a fab context, early measurements might be used to identify potentially problematic wafers for closer scrutiny at future inspection points.

Modeling edge placement error
Although process control and yield are not the same, they are of course closely related. Lithography metrics like edge placement error correlate to the yield of the finished circuit, and EPE is currently unacceptably high in leading edge processes. ASML’s Harm Dillen estimates that local CD and placement errors are the largest contributor to EPE, while overlay errors account for about one-third of the total.^⁠[3] In a more detailed analysis, Chris Mack, CTO of Fractilia, developed a model for EPE based entirely on measurable quantities.^⁠[4] As he explained, such a model can be used for lot disposition, but can also support process control decisions and error budget calculations. While Mack’s presentation focused on edge placement error in complementary lithography, he emphasized that the method can be applied more generally.

Fig. 1: In complementary lithography, the edge placement error depends on both exposures as well as the overlay between them. Source: Fractilia

Complementary lithography uses two mask exposures to define the finished pattern. Mask 1, the “line” mask, defines an array of lines and spaces. Mask 2, the “cut” mask, cuts the lines into segments.

Fig. 2: Small changes in the standard deviation of overlay can cause large changes in the process window. Source: Fractilia 

Both line and cut mask steps have some amount of error, and there is some amount of misalignment between them. If the total error is too large, the second exposure might cut the lines in the wrong place, making the segments too long or too short. The cut also might fail to completely sever the line, or might intrude on the wrong line. Because the two masks are printed separately, the errors are not necessarily correlated. The standard deviation of the final CD depends on the CDs of both the cut and the line mask, as well as the overlay error between them.

The overlay error, in turn, depends on the placement errors of both exposures as well as the overlay of the exposure system.

One of the implications of this result is that the final feature is very sensitive to overlay error. A change of a few Ångstroms in the overlay error leads to a nanometer-scale change in the process window.

Metrology is not the limiting factor
Accurate measurements of nanometer-scale features are themselves challenging. The difference between a CD-SEM roughness measurement and the actual dimensions of the feature on the wafer depend on the image acquisition conditions. Reducing the electron landing energy, for instance, helps minimize resist shrinkage, but also reduces image contrast. The goal of automated “unbiasing” tools is to make roughness measurements less contrast dependent.

Researchers at Applied Materials and imec investigated how such tools affect the relationships between roughness and other lithography metrics.^⁠[5] They found that unbiasing did not change the behavior of roughness over a focus-exposure matrix. While increasing electron landing energy increased resist shrinkage, it did not change the unbiased roughness measurements.

CD-SEM contrast also depends on the resist thickness, imec’s Gian Lorusso said, with thinner resists offering less contrast.^⁠[6]

Accurate metrology appears to require a signal-to-noise ratio of two or better. Increasing the image acquisition time — the number of frames — improves contrast, but also reduces throughput. Using programmed defects, Lorusso’s group found that breaks stay about the same size as resist thickness diminishes, while bridge defects get smaller. Thinner resists may allow more complete development of trenches. While metrology is more challenging with thinner resists, they expect roughness, not metrology, will ultimately limit achievable resolution.

Overall, this year’s SPIE Advanced Lithography and Patterning conference brought good news for advanced devices. Even at the extreme edges of the technology roadmap, process metrology and yield management tools continue to support lithographers’ efforts. However rough the advanced lithography waters might be, engineers should at least be able to see where they’re going.

¹ Franz Zach, et. al., “Multi-metrology: towards parametric yield predictions beyond EPE,” Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 124960P (27 April 2023); https://doi.org/10.1117/12.2658042

² Lilach Choona, et. al., “Direct yield prediction from SEM images,” Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 124960Q (27 April 2023); https://doi.org/10.1117/12.2658294

³ Harm Dillen, et. al., “The edge placement error characterization and optimization for advanced logic and DRAM nodes,” Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 124960O (30 April 2023); https://doi.org/10.1117/12.2658832

⁴ Chris A. Mack, Michael E. Adel, “Overlay and edge placement error metrology in the era of stochastics,” Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 1249609 (27 April 2023); https://doi.org/10.1117/12.2658735

⁵ Bobin Mathew, et. al., “Unbiased roughness measurements for 0.55NA EUV material setup,” Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 1249607 (27 April 2023); https://doi.org/10.1117/12.2658505

⁶ Gian Francesco Lorusso, et. al., “Dry resist metrology readiness for high-NA EUVL,” Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 1249612 (27 April 2023); https://doi.org/10.1117/12.2658280