Manufacturing Bits: April 21

Fan-out packaging consortium
A*STAR’s Institute of Microelectronics (IME) and others have formed a high-density fan-out wafer level packaging (FOWLP) consortium in Singapore.

Others in the group include Amkor, Nanium, STATS ChipPAC, NXP, GlobalFoundries, Kulicke & Soffa, Applied Materials, Dipsol Chemicals, JSR, KLA-Tencor, Kingyoup Optronics, Orbotech and Tokyo Ohka Kogyo (TOK).

TSMC is separately developing fan-out as well. In traditional fan-in wafer-level packages, the I/Os are situated over the solder balls. In fan-out, however, individual dies are embedded in an epoxy material. Space is allocated between each die for additional connections points, enabling higher I/O counts. Fan-out reduces the overall package height and enables more than 500 I/Os.

Nanium’s wafer-level packaging (Source: Company)

Fan-out and other technologies could bridge the gap between today’s package-on-package (PoP) packages and 2.5D/3D technology. On the other hand, fan-out could push out the need for advanced stacked die.

“High-density wafer-level fan-out packaging technology enables advanced system scaling for form factor limited and cost challenged applications,” said Ramakanth Alapati, director of package architecture and customer technology at GlobalFoundries, on A*Star’s Web site.

“This collaboration will accelerate the important development activities we have been focusing on such as ultra-thin package profiles, finer line/space widths down to 2µm/2µm and multi-layer redistribution in order to achieve smart system integration at a lower cost for our customers,” said Han Byung Joon, executive vice president and chief technology officer at STATS ChipPAC.

Fan-out is geared for mobile products and other systems. For some time, mobile products have incorporated a packaging technology called PoP, which utilizes flip-chip interconnects with ball grid array (BGA) balls on the bottom of the package.

Now, the industry wants a PoP that is smaller, thinner and provides better performance. The candidates include bond via array (BVA), embedded PoP, fan-in, fan-out, high-bandwidth PoP (HB PoP), multi-chip modules (MCMs) and through mold via (TMV).

Not all are pushing fan-out. Samsung Electronics, for one, is ramping up embedded package-on-package (ePoP) technology–a single memory package consisting of 3GB LPDDR3 DRAM, 32GB eMMC and a controller. The LPDDR3 mobile DRAM operates at an I/O data transfer rate of 1,866Mb/s, and sports a 64-bit I/O bandwidth.

Samsung’s embedded package-on-package (Source: Company)

Samsung’s smartphone ePoP does not need any space beyond the 225 square millimeters (15x15mm) taken up by the mobile application processor. Compared to traditional PoP, ePoP decreases the total area used by approximately 40%.

Not to be outdone, Intel recently announced an advanced packaging technology called Embedded Multi-die Interconnect Bridge (EMIB).

Making molybdenum disulfide
Molybdenum disulfide (MoS2) continues to generate steam in R&D. Researchers are exploring MoS2 materials for use in contacts in future FET devices. Some are also looking at MoS2-based FETs as well.

MoS2 belongs to a family of 2D materials called transition-metal dichalcogenides. They have two chalcogenide atoms for every transition-metal atom. The chalcogenide atoms include sulfur, selenium or tellurium. The transition-metal atoms include molybdenum and tungsten.

Making the material in the lab is one thing. Creating high-quality MoS2 material over large areas is difficult.
In response, A*STAR has devised a new process for synthesizing wafer-scale MoS2 atomic layers using magnetron sputtering. Magnetron sputtering, a form of physical vapor deposition (PVD), makes use of high power densities.

Transistors made of films of two-dimensional molybdenum disulfide (Source: A*STAR )

In this process, a beam of argon ions are fired at a molybdenum target in a vacuum chamber. This, in turn, ejects molybdenum atoms from the surface. These atoms react with a sulfur vapor. The atoms, in turn, are assembled onto a sapphire or silicon substrate.

Researchers discovered that the MoS2 layers are homogeneous and crystallized. The transistors composed of the MoS2 film exhibit p-type performance with an on/off current ratio of about 10(3) and hole mobility of up to around 12.2 cm2 V−1 s−1. “Traditional mechanical exfoliation methods for obtaining two-dimensional materials have limited usefulness in commercial applications, and all previous chemical methods are incompatible for integration with device fabrication,” said Shijie Wang from the A*STAR Institute of Materials Research and Engineering, on the agency’s Web site. “Our technique is a one-step process that can grow good-quality monolayer films, or few layers of molybdenum disulfide films, at wafer scale on various substrates using magnetron sputtering.”

MoS2-based RF FETs
In 2014, Kyma Technologies obtained a contract from the U.S. Army to develop MoS2 materials.

The contract also involved the incorporation of those materials in RF devices. Using a CVD reactor, the company is devising MoS2-based RF FETs. The targeted performance of these FETs is ft and fmax>5 GHz, while handling a DC power>10µW and an RF power output>1.0µW, according to the U.S. Army.

Now, Kyma will offer crystalline MoS2 materials and tools to the commercial market. Kyma’s initial efforts utilize 2-inch diameter substrates. It is focusing on the nucleation and growth of large area single monolayer MoS2 crystalline grains. So far, the highest quality triangular crystallites are located in a narrow region of the wafer.

“Our overall approach to the tool and process for growing MoS2 has been to reproduce best practices established in academia and to translate that to a commercially robust yet flexible prototype crystal growth tool,” said Kyma President and CEO Keith Evans, in a statement. “We are offering steep discounts to those customers who will help us understand our materials better and provide feedback on how we might further engineer their properties.”