Mobile Packaging Market Heats Up

Number of options for adding more features into chips grows beyond just 2.5D and 3D as mainstream packaging technologies run out of steam.


Apple, Samsung and others are developing the next wave of smartphones and tablets. OEMs want to cram more chip functions in smaller IC packages, but there are some challenges in the arena. In fact, there are signs that the mainstream packaging technology for mobiles is running out of steam.

For some time, mobile products have incorporated a technology called package-on-package (PoP), which utilizes flip-chip interconnects with ball grid array (BGA) balls on the bottom of the package. PoP is a 2D-like technology that stacks two or more separate packages on top of each other. In many cases, a memory package is on the top, while an application processor or a baseband die is on the bottom.

Now, the industry wants a PoP that is smaller, thinner and provides better performance. “(PoP) is approaching its limits,” said Raj Pendse, vice president and chief marketing officer at STATS ChipPAC. “Traditional packages seemed to be plateauing at somewhere between thicknesses of 0.5mm to 0.4mm. It is very hard to push the thickness below that.”

Seeking to displace today’s PoP package, several vendors currently are developing a new and competitive array of next-generation PoP technologies. It’s a confusing list of acronyms. The 2D-like PoP candidates include bond via array (BVA), embedded PoP, fan-in, fan-out, high-bandwidth PoP (HB PoP), multi-chip modules (MCMs) and through mold via (TMV).

Adding to the confusion is that some of the next-generation, 2D-based PoP schemes are also being touted as alternatives to advanced 2.5D/3D stacked die. Many next-generation PoPs have some of the same characteristics as 2.5D/3D stacked die, but whether they are true 3D packages is debatable.

Down the road, 3D-based stacked die technologies such as Wide I/O-2 are also in the running to replace the traditional PoP for mobile products. 2.5D/3D chips make use of through-silicon vias (TSVs), whether the TSVs run through a die or a separate interposer die in 2.5D chips. But advanced 2.5D/3D chip stacking has a number of challenges and is still a few years away from mass production.

Needless to say, it’s a difficult task to sort through the various technologies, and hype, in the PoP segment. For packaging engineers, the questions are obvious. Will the traditional 2D-based PoP package run out of gas? If so, what’s next? And where does 2.5D/3D technology fit in the scheme of things?

As before, packaging boils down to the usual criteria—application type; performance; and cost. “The near term choices for mobile devices are not 3D ICs, but rather PoP,” said Jan Vardaman, president of TechSearch International, a market research firm. “PoP could include flip-chip die, a fan-out wafer-level package in the bottom package, or an embedded die in the bottom laminate package of the PoP structure. It is possible that there could be some stacked die with a TSV in the memory package on the top, but not in the near turn. Stacking logic and memory with TSVs remains problematic.”

Right now, it appears that one technology is taking a slight lead in the next-generation PoP sweepstakes—fan-out wafer-level packaging (FO-WLP). “FO-WLP is here now,” Vardaman said. “This is a package that is mainly used in wireless products such as mobile phones, although there are some automotive applications such as radar. It does not compete with the applications in the high-end that will use 2.5D and 3D ICs.”

Noise in PoP market
Today’s flip-chip PoP is used to stack mobile DRAMs and logic in smartphones and tablets. In recent times, the explosion of data and video has caused a memory bandwidth bottleneck in mobiles. To keep up with the bandwidth requirements, mobile DRAMs are migrating from the LPDDR3 to the LPDDR4 interface standard. In total, LPDDR3-based mobile DRAMs feature bandwidths between 7.5- to 15-GB/s. LPDDR4 boasts a bandwidth from 12.8- to 25.6-GB/s. Both LPDDR3- and LPDDR4-based mobile DRAMs are housed in a traditional PoP.

Still, consumers want more bandwidth. So following LPDDR4, the industry will likely go in two directions at once—2D and 3D. Memory makers could take the evolutionary path and develop LPDDR5 technology, which would come in a 2D-like PoP. At the same time, memory makers will continue to develop the more radical, 3D-based Wide I/O-2 chips for mobile products. Wide I/O-2 has a bandwidth from 25.6- to 51.2-GB/s.

Wide I/O-2 devices are expected to sample in 2015, but the technology is expected to be an expensive solution, at least initially. So for the foreseeable future, 2D-based PoP will be used for mobile products due to cost.

But if the industry extends today’s PoP for mobile products, then OEMs face some challenges. The maximum height of today’s PoP packages is typically 1.4mm to 1.6mm, but the eventual goal is to drive the dimensions down to 1mm and below. And the PCB substrate technology limits the interconnection density of a PoP from 200 to 300 I/Os.

So, if or when today’s flip-chip PoP hits the wall, what’s next? There are a multitude of options in the 2D space, including new wire-bonding schemes and embedded technologies. “There is more than one way to skin a cat,” STATS ChipPAC’s Pendse said.

In one option, the industry could try and shrink flip-chip PoP. On the wire-bonding front, Invensas is pushing a PoP scheme called Bond Via Array (BVA). Using a freestanding wire-bond technology, BVA enables more than 1,000 interconnects at a 0.24mm pitch.

Still, the momentum is swinging towards embedded packaging technologies. Advanced Semiconductor Engineering (ASE) and others are pushing one form of the technology, dubbed embedded PoP. In embedded PoP, chips and/or passive components are embedded in a built-up substrate in the bottom of the package. The electrical contacts consist of tiny micro-vias, which are formed by laser drilling.

Embedded PoP enables a smaller package with shorter electrical connections. It also requires longer assembly times and good substrate technology, according to TechSearch. Embedded PoP require bare die, which is sometimes difficult to handle and test.

“ASE supports both evolutionary technologies in packaged PoP solutions, as well as some pseudo embedded technologies that we refer to as HB PoP or High- Bandwidth PoP,” said Rich Rice, senior vice president of business development at ASE US.

Another form of embedded is FO-WLP, which is gathering steam in the market. In traditional fan-in WLP, the I/Os are situated over the solder balls. In FO-WLP, however, individual dies are embedded in an epoxy material. Space is allocated between each die for additional connections points, enabling higher I/O counts.

FO-WLP reduces the overall package height and enables more than 500 I/Os. And it has some advantages over today’s flip-chip PoP. “Bumping and the substrate are typically on the order of 60% to 70% of the total cost of a flip-chip package,” STAT ChipPAC’s Pendse said. “[With FO-WLP] you basically eliminate those costs, but you have the cost in processing the thin-film layers. In the end, it can be anywhere from 25% to 50% cheaper.”

On the down side, FO-WLP requires different tools and materials. For some time, Infineon and STATS ChipPAC have been developing FO-WLP, but the technology is taking longer to get off the ground than previously thought. But recently, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) entered the FO-WLP packaging market, which could help propel the technology into the mainstream. TSMC refers to its FO-WLP technology as InFO-WLP.

“We look at TSMC as an endorsement of what we are doing,” said Pendse said. “At some point, we will compete with TSMC.”

For some time, TSMC has been expanding into the traditional IC-packaging market, as part of an effort to offer more products and services for customers. “InFO-WLP can do chip partitioning,” said Doug Yu, senior director of the integrated interconnect and packaging program at TSMC. “(InFO-WLP) not only covers mobile applications, but it also can be applied to higher performance applications.”

The initial versions of FO-WLP are 2D packages, but the technology can be configured into 2.5D/3D-like versions. For example, STATS ChipPAC offers a face-to-face configuration. In this scheme, there is a direct vertical interconnection between an application processor die and a memory die through a mold layer. “(FO-WLP) provides an alternative to TSV-based solutions, which are becoming harder due to cost and the infrastructure,” Pendse said.

What about 3D?
This is where the confusion starts. BVA, embedded PoP, FO-WLP and other 2D schemes can resemble 2.5D/3D-like packages, but these technologies aren’t true 3D schemes based on the strict sense of the term.

The real question is less obvious. Will embedded PoP and FO-WLP push out the need for 3D-based Wide I/O-2 in the mobile market? “That’s possible,” said ASE’s Rice. “There are various technologies that are PCB- or wafer-based, which enable a higher density PoP solution by providing enough interconnects for the LPDDR4 interface. Current PoP technologies that are assembly-based are also advancing to offer higher bandwidth memory interfaces.”

3D-based Wide I/O-2 technology remains promising for mobile products, but the industry must address several issues before the devices are ready for prime time. “TSV is not new,” said Issac Ow, global product manager at Applied Materials. “They have been used in MEMS or in CMOS image sensors. But overall, the volumes (for 2.5D/3D TSV chips) are not that high yet. We all know what’s driving the industry. It’s mobility. One item on the list of things to do is still about cost and cost for volume production.”

In fact, the sheer cost of the technology has relegated the current 2.5D/3D TSV devices to high-end applications. On the manufacturing front, for example, 3D TSV technology adds 15% or more in terms of total wafer processing costs, compared to a traditional planar flow, according to data from North Carolina State University.

The front-side, via-middle TSV processing steps represent the most expensive part of the 2.5D/3D flow. In order, the TSV production flow includes the following steps: TSV etch; CVD liner; PVD barrier and seed; TSV copper plating; and polishing, according to Applied Materials.

To address the PVD piece of the puzzle, Applied Materials recently rolled out the Ventura PVD system, a dedicated PVD tool that promises to lower TSV costs. The tool enables traditional tantalum barrier production. It also supports the use of titanium as an alternate barrier material for lower cost. “TSVs have scaled to 10:1 or more aspect ratios,” Ow said. “But existing copper interconnect PVD technology is not able to address barrier seed deposition in a cost effective manner.”

Over time, 2.5D/3D-based chips will come down in price and spread into new markets. In addition, the traditional 2D packages are moving up and will have more 3D-like characteristics. So which technology—2D or 2.5D/3D—will prevail in the market in the long term? “They will all co-exist,” Ow said. “It really depends on the end product versus the cost and the desired performance.”

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