Manufacturing Bits: Dec. 14

3D-SOCs
At this week’s IEEE International Electron Devices Meeting (IEDM), a plethora of companies, R&D organizations and universities presented papers on the latest and greatest technologies.

One of the themes at IEDM is advanced packaging, a technology enables an IC vendor to boost the performance of a chip. Advanced forms of packaging also enables new 3D-like chip architectures.

For example, at IEDM, Imec presented a paper on “3D-SOC integration, beyond 2.5D chiplets.” 3D-SOCs is one way to improve the performance in systems.

Traditionally, to advance a design, vendors would develop a system-on-a-chip (SoC) and integrate more functions on the device at each generation. But this is becoming more difficult and expensive at each turn. While this method remains an option for new designs, chiplets promise to be the next big thing.

For chiplets, a chipmaker may have a menu of modular dies in a library. Customers then can mix-and-match the chiplets and integrate them in an existing package type or new architectures. In these architectures, the dies are connected using various die-to-die interconnects.

For example, a memory stack is connected to a processor chip through an interface bus. But the interfaces are prone to latency, preventing fast access between the chips.

There is a solution. On the design side, a 3D-SOC requires a co-design strategy with new EDA tools, according to Imec. Then, on the manufacturing side, wafer-to-wafer hybrid bonding is used to enable fast chip-to-chip interconnects, according to the R&D organization.

Targeted for 10μm pitches and below, hybrid bonding connects dies in packages using tiny copper-to-copper connections. It provides more interconnect density, enabling 3D-like packages and advanced memory cubes. But hybrid bonding also adds some challenges in the fab.

With 3D-SOC integration, memory-logic partitions can be realized using direct and shorter interconnects, according to Imec. In the paper, Imec demonstrated an optimized implementation of a 3D-SOC design with memory macros in the top die and remaining logic in the bottom die – resulting in a 40% higher operating frequency compared to a 2D design. The two dies are connected using a low-temperature wafer-to-wafer bonding technique.

“On the design side, a 3D-SOC co-design strategy is needed for both logic and memory partitions. This requires dedicated electronic design automation (EDA) tools that can handle both designs simultaneously, using automated tools for system partitioning and 3D critical path optimization during place-and-route. Through our collaboration with Cadence, we have access to these highly advanced tools,” said Dragomir Milojevic, a principal scientist at Imec and professor at Université libre de Bruxelles.

3D-ICs, hybrid bonding standards
At IEDM, Intel presented a paper, saying it developed several test chips using copper hybrid bonding. At the same time, Intel is also calling for the establishment of new industry standards and testing procedures to enable a hybrid bonding chiplet ecosystem.

Besides hybrid bonding, Intel presented papers on other technologies at IEDM as well. Meanwhile, using hybrid bonding, Intel developed an 3D-IC test chip that stacks an SRAM top die on a SRAM base die. This in turn creates a 3D SRAM. The dies are connected using hybrid bonding.

In the basic hybrid bonding flow, a wafer is processed and then the metal pads are recessed on the surface. The surface is planarized and then activated.

A separate wafer undergoes a similar process. The wafers are bonded using a two-step process. It’s a dielectric-to-dielectric bond, followed by a metal-to-metal connection.

“Hybrid bonding enables interconnects densities comparable to monolithic interconnects which opens the door to many new architectures. We reviewed the design, wafer processing and assembly requirements to enable hybrid bonding on Intel processes. The process development is compatible with future Intel processes. We highlighted some of the design, process and assembly challenges and our solutions to address them,” said Adel Elsherbini, a senior principal engineer at Intel, who was the lead author of the paper. Others contributed to the work.

In the same paper, Intel addressed other key issues with hybrid bonding. “There are many new challenges that need to be addressed and new standards to be developed. For example, testing at such fine pitch is extremely challenging and novel test techniques and standards are needed. Additionally, unlike solder assembly, hybrid bonding requires several additional new requirements on the bonding layer, and die properties such as flatness, and tolerance to process temperatures. This requires new standards to enable a hybrid bonding chiplet ecosystem such that chiplets from several foundries and process nodes may be assembled to each other,” Elsherbini said.