Manufacturing Bits: Dec. 16

Space DSA
NASA’s Physical Science Research Program is taking directed self-assembly (DSA) technology to new heights.

On the International Space Station, astronauts are exploring the development of nanoparticles suspended in magnetorheolocial (MR) fluids. MR fluids, which are a new class of smart materials, self-assemble into shapes in the presence of a magnetic field. With the technology, researchers hope to find new ways of making materials, such as small colloidal or nanoparticle building blocks.

The experiment is part of NASA’s so-called Investigating the Structure of Paramagnetic Aggregates from Colloidal Emulsions (InSPACE) program. Astronauts conducted the experiments in a contraption called the Microgravity Science Glovebox (MSG), which is located in the European Space Agency’s Columbus laboratory module. The MSG is designed to accommodate experiments in a workbench type environment.

European Space Agency (ESA) astronaut activates the Microgravity Science Glovebox for DSA experiment. (Source: NASA)

In the experiment, MR fluids can transition into a nearly solid-like state when exposed to magnetic fields. The fluids disassemble and buckle when the magnetic field is removed. In fact, the solid columns expand axially and buckle laterally. “There’s a growing interest in buckling phenomena in terms of manipulating, in particular, soft materials,” said Eric Furst of the University of Delaware, on NASA’s Web site. “Whether we want to induce bucking or not, I’m not sure. That’s the engineering question we have in front of us.”

Bob Green, an InSPACE project scientist at NASA’s Glenn Research Center in Cleveland, added: “This is a fundamental experiment to develop techniques that could potentially make new materials that cannot be fabricated using conventional methods. With directed self-assembly, you can manipulate the structure of a material on a nanoscale in such a way as to form a new material that has unique properties.”

Intel’s BIST engine
At the recent International Test Conference (ITC), Intel, Georgia Tech and Oregon State University described a new built-in-self-test (BIST) architecture.

The technology, dubbed the Converged-Pattern-Generator-Checker (CPGC), is incorporated within Intel’s 14nm technology. The CPGC is designed to detect memory and I/O defects. But combined with a software assisted repair technology, CPGC could be used to automatically repair memory cell defects on 3D stacked Wide-IO DRAM.

“CPGC can speed up validation by 5x, improve test time from minutes down to seconds, and decrease debug time by 5x including root-cause of boot failures of the memory interface,” according to the ITC paper.

The intellectual-property (IP) of the CPGC is embedded in a memory controller. Compared to Intel’s Atom S1200 die area of 9.86- x 10-mm, the BIST engine occupies 0.045% of total area. It has a total active power of 5.8mW.

“Functional traffic from the SOC core that originates from upstream is multiplexed with CPGC to form the command and data of the DDR protocol. It is transmitted through the memory scheduler and data-buffer to the DDR I/O. CPGC control registers are programmed through a standard low bandwidth interface, and an out of band protocol interface exists between CPGC and DDR I/O,” according to the paper.

A key to the technology is a reusable BIST engine. “After CPGC detects memory failures, it supports both manual and automatic modes depending on the software configuration to repair the defective cell using the spare cells that the DRAM manufacturer provided,” the paper said.

Testing military chips
Under DARPA’s Integrity and Reliability of Integrated Circuits program, the Naval Surface Warfare Center (NSWC) and the Air Force Research Laboratory (AFRL) are collaborating in the development of a testing methodology for military chips.

The trio have devised a virtual lab. The lab consists of a CAD-based file-sharing environment for use in transferring data in chip analysis and debugging.

DARPA’s virtual lab is also creating new hardware methods to test, analyze and repair chips. One test uses advanced failure analysis tools. Traditionally, focused ion beam (FIB) tools are used, but this technology could end up destructing a chip. Instead, researchers devised a proprietary, non-destructive technique. The non-invasive testing was conducted using a 1340nm laser to alter the chip’s circuitry.

“Integrated circuits or microchips form the backbone of all military IT and electronics systems, and ensuring that these microchips are free from unauthorized tampering is essential to national security. Unfortunately, this task has become increasingly difficult as more microchips are designed and built around the world in commercial facilities,” said Kerry Bernstein, DARPA program manager, on the agency’s Web site. “Improving chip intrusion detection and assessment speed across the investigative community will help prevent the installation of counterfeit chips in military systems and enhance overall confidence in the electronics supply chain.”

The key is collaborating with the various services. “Given how widespread microchips are, and their vulnerability to compromise, the numbers don’t seem to be on our side,” Bernstein said. “Through the virtual lab, however, we can help shift the balance in our favor. By extending testing resources to our service partners and working together more effectively, we can ensure the reliability of our most important electronic systems.”

Under the auspices of DARPA, the Naval Surface Warfare Center (NSWC) and Air Force Research Laboratory (AFRL) are collaborating in new ways to determine the reliability and integrity of microchips embedded in critical military weapon and cyber systems. (Source: DARPA)