Manufacturing Bits: Dec. 23

Higgs boson sensors
At the recent 2014 IEEE International Electron Devices Meeting (IEDM) in San Francisco, CERN described the tiny hybrid pixel detectors used at the Large Hadron Collider (LHC). Using CMOS technology, hybrid pixel detectors identify and tag individual sub-atomic particles at fast speeds.

CERN, the European Organization for Nuclear Research, is a particle physics laboratory that is situated at the Franco-Swiss border near Geneva, Switzerland. The lab consists of the LHC, a giant, 27-kilometer particle accelerator.

In 2012, researchers from CERN observed the Higgs boson, an elementary sub-atomic particle. This particle is consistent with the Higgs boson predicted by the Standard Model of particle physics. Elementary particles may have gained their mass from the elusive Higgs boson particle.

To find Higgs boson, researchers used two giant detectors within the LHC—Atlas and CMS. From a cavern 100 meters below a small Swiss village, the 7,000-ton Atlas detector is also exploring the existence of extra dimensions and particles that could make up dark matter. In operation, beams of particles from the LHC collide at the center of the Atlas detector. This, in turn, causes particles to fly in all directions. Six different detecting subsystems record the paths and energy of the particles.

Atlas is one of two general-purpose detectors at the Large Hadron Collider. It was used to find the Higgs boson particle. (Source: CERN)

The CMS detector, meanwhile, is built around a huge solenoid magnet. This takes the form of a cylindrical coil of superconducting cable that generates a field of four tesla, or about 100,000 times the magnetic field of the Earth, according to CERN.

To find Higgs boson and other particles, researchers made use of smaller hybrid pixel detectors. “Every 25 or 50ns bunches of protons are made to collide in the heart of the experiments and on average 20-30 proton interactions take place generating thousands of debris particles. In searching for the Higgs boson, the particles produced in a given interaction need to be detected and tagged to a given bunch crossing (BC),” according to a paper from CERN at IEDM. “In the innermost regions of the detector the trajectory of charged particles must be recorded as precisely as possible.”

The LHC does not use standard CCDs or CMOS image sensors, which could not survive the doses of radiation in the various experiments. Instead, researchers use hybrid pixel detectors, which are based on advanced CMOS circuitry. “The basic building block of a hybrid pixel detector is the combination of a monolithic matrix of reverse biased silicon diodes connected using high density bump bonding to a number of large area CMOS readout ASICs,” according to the CERN paper at IEDM. “Each individual sensor diode is connected using a solder bump to its own mixed-mode readout circuit on the ASIC side.”

The sensor itself is made of a high resistivity material. The device allows all of the charge generated during one particle traversal to be collected within ~15ns. “Probably the most important feature of hybrid pixel detectors is their ability to provide practically noise free ‘images’ of each BC. Analyzing each ‘image’ or ‘frame’ it is possible to disentangle the (on average) 20-30 simultaneously occurring events from each other,” according to the paper.

Each experiment uses a different sensor. In the Atlas experiment, for example, a pixelated sensor is connected using micro-bumps to 16 ASIC readout chips. Each chip contains thousands of readout channels each measuring 50μm x 400μm.

The hybrid pixel ASICs are based on a 250nm CMOS process, but finer geometries are being explored. “In the case of the upgrades for Atlas and CMS, the aim is to use reduced chip and sensor thicknesses, at the same time modifying the readout ASIC architectures to be able to deal with the higher particle fluxes expected from the upgraded LHC accelerator,” according to the paper. “The aim is to use ultra-thin monolithic devices where the sensor and readout circuits are incorporated onto the same substrate, making use of special semiconductor processes which were developed for CMOS sensors.”

Nano tweezers
The University of Tokyo used IEDM to describe the development of a tiny MEMS-based tweezer technology with sharp tips. The tweezers were able to capture a bundle of DNA molecules and allow real time observation of DNA.

The MEMS-based tweezers, dubbed silicon nano tweezers (SNT), were composed of a pair of probes with a 10nm to 50nm tip radius. They were integrated with micro actuators for handling DNA molecules. In addition, the tweezer is integrated on a chip. The chip consists of an array of fL-chambers. In each chamber, a single enzyme molecule was captured.

The small size of MEMS structure allowed the detection of enzymatic activity of a single molecule. The chip can distinguish normal and abnormal tau-proteins related to Alzheimer’s disease.

In the lab, researchers conducted the real-time biomechanical measurement of the degradation of DNA. The experiments were performed with Cyberknife, a LINAC accelerator mounted on a robot arm at the Centre Oscar Lambret in Lille, France, according to the paper at IEDM.

Accuray’s CyberKnife System provides full-body surgery using robots. “After capturing a DNA bundle, SNT’s tips are placed inside a microfluidic cavity; the alignment and the insertion are controlled by a micro-robot,” according to the paper. “The collimated beam, delivering an intense 6 MeV photon flux, completely encompasses the SNT holding the DNA bundle in the microfluidic cavity.”

Castle chips for RF apps
Also at IEDM, Northrop Grumman described a transistor structure, based on a gallium nitride (GaN), super-lattice channel with a 3D gate. The transistor, dubbed the SLCFET (Super-Lattice Castellated Field Effect Transistor), is geared for RF applications.

Super-lattice structures have been developed in the past, but the use of a super-lattice channel for a FET has been limited, according to researchers. The solution to the problem, according to Northrop Grumman, is to develop a “castellated gate structure.” The architecture resembles a medieval castle wall with turrets and battlements.

The SLCFET, in turn, “allows the electric field applied by the gate to penetrate into each of the stacked 2DEG channels by means of the sidewalls of the three dimensional gate structure,” according to the paper at IEDM. “The super-lattice creates multiple current channels in parallel between the source and drain of the device, lowering ON resistance.”

In the lab, the transistor measurements provided median values of IMAX>2.7 A/mm, VPINCH = -8V, with RON=0.41 Ω-mm and COFF=0.19 pF/mm, for an RF switch FOM of FCO=2.1 THz.

The SLCFET is based on a super-lattice of AlGaN/GaN heterojunctions. It is fabricated on 100mm diameter silicon carbide wafer using an MOCVD process. “The SLCFET transistors fabrication process uses a combination of I-line stepper and electron beam lithography processes, resulting in a direct written 0.25μm ‘brick’ gate,” according to the paper. “The castellated, three dimensional gate is formed using a series of trenches created using a dry etch process of the AlGaN/GaN super-lattice, on top of which the gate is overlaid.”