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Manufacturing Bits: Dec. 31

GaN-on-SOI power semis; SiC channel boosters.

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GaN-on-SOI power semis
At the recent IEEE International Electron Devices Meeting (IEDM), Imec and KU Leuven presented a paper on a gallium-nitride (GaN) on silicon-on-insulator (SOI) technology for use in developing GaN power devices.

With GaN-on-SOI technology, researchers have developed a 200-volt GaN power semiconductor device with an integrated driver and fast switching performance.

GaN, a binary III-V material, is a wide-bandgap technology, meaning it is faster and more efficient than silicon-based power devices. GaN has 10 times the breakdown field strength with double the electron mobility than silicon.

In one GaN power semi flow, a thin layer of aluminum nitride (AlN) is deposited on a silicon substrate. A GaN layer is grown on the AlN layer. A source, gate and drain are formed on the GaN layer, forming a GaN power semi.

GaN semis are targeted for different markets. Some vendors compete in the lower voltage segments from 15 to 200 volts. Others compete in the 600-, 650-, and 900-volt markets.

GaN power semis face some challenges. “All-GaN power ICs require various modules including half-bridge, diode, capacitor, driver, dead-time control, level shifter, pulse width modulation (PWM), diagnostic and protection circuit, regulator, bandgap reference, bootstrap circuit, etc. Many efforts have been made to integrate those single or multiple modules on GaN-on-Si (silicon),” said Xiangdong Li from Imec in the IEDM paper. “However, the challenge for all-GaN ICs on a traditional Si substrate is firstly the lack of effective isolation, which induces a back-gating effect in the half-bridge; secondly, the absence of GaN pFET, which is a bottleneck for integrating high-performance logic circuits.”

This is where GaN-on-SOI fits in. “GaN-on-SOI with deep trench isolation is promising for GaN power integrated circuits (ICs), highlighting the advantages of the eliminated back-gating effect, effective isolation, suppressed parasitic inductance, and reduced area,” Li said.

For this technology, researchers used a 200mm SOI substrate. Using metalorganic chemical vapor deposition (MOCVD), Imec and KU Leuven developed a stack on the SOI substrate. The stack consisted of a 200nm AlN nucleation layer, a 3.25μm AlGaN buffer layer, a 400nm GaN channel layer, a 12.5nm AlGaN barrier layer, and an 80nm Mg-doped p-GaN layer, according to researchers.

“Different components of HEMT, SBD, MIM capacitor, 2D resistor, and RTL logic have been successfully co-integrated on this platform,” Li said. “A demonstrator 200-V half-bridge and 48V-to-1V single-stage buck converter GaN ICs validated the functionality of this technology platform.”

SiC channel boosters
At IEDM, Mitsubishi and the University of Tokyo presented a paper on improving the channel performance of a silicon carbide (SiC) MOSFET.

Researchers used a new oxygen doping technique to boost the performance of SiC MOSFETs.

Like GaN, SiC is a wide-bandgap material, making it ideal for fast, efficient power semiconductor applications. SiC is a compound semiconductor material based on silicon and carbon. It has 10 times the breakdown field strength and 3 times better thermal conductivity than silicon.

“Generally power electric systems require both low Ron and high Vth. Low Ron contributes to energy loss reduction, and high Vth provides their better controllability. To achieve relatively low channel resistance (Rch), a nitridation process is usually used in the industry because this technique realizes sufficient stability of Vth against positive and/or negative bias temperature stresses. Other gate oxidation processes help lower Rch, but the resulting Vth stability is less stable than that for nitridation,” said Noguchi Munetaka from Mitsubishi in the IEDM paper.

“On the other hand, it has been reported that there is a severe trade-off relationship between Rch and Vth for Si-face 4H-SiC MOSFETs treated by nitridation where Rch increases severely in the high Vth region over 3 V. This feature suggests that more than a half of Rch can be reduced in the high Vth region if this trade-off relationship can be shifted by +1.2 V,” Munetaka said.

Researchers have proposed a new channel engineering technique to break this trade-off. They demonstrated a SiC MOSFET with oxygen doping in the channel region.

“Compared with a conventional device, the O-doped channel was found to provide lower channel resistance (Rch) and higher threshold voltage (Vth), which is expected from the fact that O acts as a deep level donor in 4H-SiC,” Munetaka said. “By applying this novel technique to vertical 4H-SiC MOSFETs, 32% reduction of specific on resistance (Ron) at a high Vth of 4.5 V was achieved.”



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