Manufacturing Bits: Feb. 16

Hybrid bonding consortium for packaging
A*STAR’s Institute of Microelectronics (IME) and several companies have formed a new consortium to propel the development of hybrid bonding technology for chip-packaging applications.

The group, called the Chip-to-Wafer (C2W) Hybrid Bonding Consortium, includes A*STAR’s IME organization, Applied Materials, ASM Pacific, Capcon, HD MicroSystems, ONTOS Equipment Systems, Panasonic, Sekisui, Toray and Yamaha.

Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages.

Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides more bandwidth with lower power than the existing methods of stacking and bonding. But hybrid bonding also is more difficult to implement.

Led by Singapore’s A*STAR, the new consortium plans to develop chip-to-wafer hybrid bonding technologies for high-density 2.5D/3D packages.

Device manufacturers will contribute to the design, process and reliability requirements, whereas the equipment suppliers will contribute by developing new tools and capabilities. Material suppliers will bring along new dielectric materials for hybrid bonding as well as temporary adhesives for thin wafer handling.

The goal is to demonstrate a four-chip stacking technology with ≤10um pitch interconnections. “Breakthroughs by C2W hybrid bonding technology will allow device manufacturers to better integrate 2.5D/3D products with high added value, such as memory stack, logic and memory system-in-package, and chiplets,” according to A*STAR. “Such technologies could open up new business opportunities for not only device manufacturers, but also equipment suppliers and material suppliers related to hybrid bonding and process integration technologies.”

Quantum interposers
CEA-Leti, CEA-List and Néel Institute at the French National Centre for Scientific Research (CNRS) have developed an interposer that enables the integration of devices for quantum computing.

The technology, known as QuIC3 or quantum integrated circuits with CryoCMOS, is based on a silicon interposer. The interposer accommodates and connects quantum chips and control chips in systems.

Quantum computing is different than today’s computers. In classical computing, the information is stored in bits, which can be either a “0” or “1”. In quantum computing, information is stored in quantum bits, or qubits, which can exist as a “0” or “1” or a combination of both.

The superposition state enables a quantum computer to perform millions of calculations at once, enabling it to outperform a traditional system. But quantum computing is still in its infancy and has a long way to go.

The industry is developing different types of quantum computing devices. One of the more challenging aspects of quantum computing is to scale up the qubits in a system.

It is also difficult to maintain the quality of qubits used to perform quantum computing calculations. Qubits lose their properties, typically within 100 microseconds, due in part to the interconnected machinery’s ambient noise of vibrations, temperature fluctuations, and electromagnetic waves, according to IBM.

Leti, meanwhile, has been developing silicon-based qubits. As part of those efforts, Leti has developed an interposer for the development of devices in quantum computing.

The interposer’s purpose is to connect quantum chips containing qubits and control chips, and to address and read the qubits, with two metal levels on the front-side of the interposers. Additional on-chip circuits integrated on the interposer provide alternative reading options of information stored in the qubits. Passive elements and filter devices could be integrated on the interposer.

The prototype interposer controls quantum chips by embedding control electronics near the quantum chip inside a dilution cryostat at T<1K. This temperature range is required for reliable operation of qubits.

Quantum chips and the control electronics are integrated on the interposer using a 3D flip-chip process. The control electronics are fabricated on standard FDSOI 28nm-node technology and manufactured by STMicroelectronics.

“Realization of a QuIC3 demonstrator for 3D co-integration of quantum chips with CryoCMOS FDSOI 28nm control chips is an important step toward a full quantum computing system that operates at a very low temperature, less than 1 K, with optimum control and reading performance,” said Maud Vinet, head of CEA-Leti’s quantum computing program.

In a separate development, a European consortium was launched with the goal of scaling silicon quantum technologies. Named QLSI (Quantum Large-Scale Integration with Silicon), this four-year EU project, coordinated by CEA-Leti, will lay the foundation for the EU’s industrial-scale implementation of semiconductor quantum processors.