Manufacturing Bits: Jan. 6

Vertical SiC chips for electric cars
Silicon carbide (SiC) is a promising material for power electronics. The material has a high breakdown voltage, high operating temperatures and a superior thermal conductivity.

At the recent 2014 IEEE International Electron Devices Meeting (IEDM) in San Francisco, Toyota, the National Institute of Advanced Industrial Science and Technology (AIST) and the University of Yamanashi presented a paper on a new vertical JFET based on SiC technology.

The device, dubbed the Screen Grid VJFET (SG-VJFET), is a promising candidate to improve the performance of power conversion systems in hybrid electric vehicles (HEVs) and electric vehicles (EVs).

Vertical SiC-based power MOFETs have several advantages over traditional lateral SiC MOSFETs. “SiC MOSFETs suffer from large Crss because of the thin depletion layer width due to the high impurity concentration of the drift layer,” according to the paper.

Toyota and others proposed a SiC-based VJFET, built around a so-called buried gate static induction transistor (BGSIT). “A major feature of the new VJFET is the p+ screen grid, the fourth electrode, located between gate and drain. This electrode is usually connected with the source electrode. It reduces the feedback capacitance Crss due to the decrease in capacitive coupling between gate and drain,” according to the paper. “On the other hand, the screen grid restricts the current flow to narrow regions, so it leads to increase the on-resistance. In order to suppress this effect, current spreading layer, which is the n-type high impurity concentration layer, is introduced between p+ gate and screen grid.”

Using a device simulator, the SG-VJFET had the highest switching speed and the lowest switching loss, compared to traditional SiC MOSFETs and VJFETs. The device reduces the Crss by 80% compared to conventional VJFETs. A blocking voltage of > 1400 Volts has been realized even at zero gate bias VGS=0 V.

Black phosphorus FETs
Two-dimensional materials are gaining steam in R&D. The 2D materials include graphene, boron nitride (BN) and the transition-metal dichalcogenides (TMDs). All told, the 2D materials could one day enable fast and low-power field-effect transistors (FETs).

A new 2D material–black phosphorus–is another promising candidate, according to Purdue University, which presented a paper on the subject at IEDM. Using this material, researchers have demonstrated photodetectors with a record photoresponsivity (223mA/W). One day, chipmakers could even make black phosphorus FETs.

Black phosphorus is a stack of monolayers with a puckered honeycomb structure. Black phosphorus has a high hole mobility (>10000 cm2/Vs) and thickness-dependent direct bandgap. The bandgap (~0.3 eV or more) of a few-layer black phosphorus structure enables an ON/OFF ratio of >105 in FETs, and it has a hole mobility of up to ~1000 cm2/Vs at room temperature, according to researchers.

In the process flow, black phosphorus flakes were mechanically exfoliated from a bulk material. They were place on a p+ doped silicon substrate capped with a 90nm SiO2. Direct-write electron beam lithography was used to define the contact patterns. Metal contacts were formed by an electron-beam evaporation and a lift-off process.

“Two different metals were used as contact metals to form two FETs on the same flake, negating the effect of flake-to-flake variability. Aluminum (4.1 eV), titanium (4.3 eV) and palladium (5.1 eV) were used as metal contacts. The thicknesses of the flakes varied from 5 nm to 20 nm as determined by atomic force microscopy (AFM), according to the paper.

“The device on the same flake using Ti as contacts shows a relatively lower on-state current under the same bias conditions,” according to the paper. “Moreover, the devices with Pd as contacts always show larger current no matter how we change the order of metal deposition.”

2D contact materials
Another 2D material, molybdenum diselenide (MoSe2), is also an attractive material for use in future FETs. MoSe2 has several properties, including a non-zero band gap, atomic scale thickness and pristine interfaces.

But there are a multitude of challenges in developing MoSe2 FETs. Obtaining a low contact resistance for 2D materials is a big challenge. It is also difficult to inject dopants into 2D materials.

At IEDM, the Gwangju Institute of Science and Technology (GIST) and Incheon National University presented a paper on the subject. Researchers described a process in which thin Al2O3 and TiO2 layers were inserted between contact metals and a MoSe2 channel as a de-pinning layer.

The contact resistance of MoSe2 FETs has been reduced by five times from the reference data using a TiO2 Fermi level de-pinning layer, which reduced the Schottky barrier height to 0.1 eV. After the optimization of the interface dielectric layer, the contact resistance of MoSe2 FETs was reduced to ~5.4 kΩ•μm, according to researchers.

In the process flow, researchers started with an exfoliated MoSe2 layer on a silicon substrate. Then, an interface dielectric layer is deposited using atomic layer deposition (ALD). This is followed by an annealing process at 600 degrees C for five minutes. Then, the source and drain contact metals are deposited using physical vapor deposition (PVD). The source and drain are based on titanium (50nm) and gold (5nm), respectively.

“SEM photographs show that the coverage of ALD-deposited Al2O3 and TiO2 layer on MoS2 is improved as the thickness of interlayer increases to 2nm,” according to the paper. “The best contact resistance and drain current are ~5.4 kΩ•μm and ~2.51 μA/μm, respectively. This contact resistance reduction is attributed to the barrier height decrease and dipole effects.”