Manufacturing Bits: June 10

Predicting warpage in packages
At the recent IEEE Electronic Components and Technology Conference (ECTC) in Las Vegas, there were several papers on ways to predict variation and warpage in IC packages.

Advanced packages are prone to unwanted warpage during the process flow. The warpage challenges escalate as the packages become thinner. Warpage in turn can impact yields in IC packages.

At ECTC, the Agency for Science, Technology and Research (A*STAR) presented a paper that studied and simulated the warpage issues for a fan-out panel-level process (FO-PLP). For this work, A*STAR conducted the study using a die last approach for a FO-PLP technology with a Gen-3 glass substrate. A Gen-3 panel measures 650mm X 550mm.

In production for several years, today’s fan-out wafer-level packaging (FO-WLP) technologies involve packaging a die in a round wafer format in 200mm or 300mm wafer sizes. In panel-level fan-out, the package is processed on a large square panel. By increasing the number of die per substrate, a vendor could see huge productivity gains and lower costs over today’s fan-out processes.

“It is known that wafer warpage is one of the critical challenges for FO-WLP technology. Such challenges will become more severe for FO-PLP technology due to the large panel size,” said F. X. Che from A*STAR in a paper at ECTC. Others contributed to the work.

A*STAR used finite element analysis (FEA) modeling to study the warpage issues in panel-level fan-out. In simple terms, FEA is a numerical method for solving problems. More specifically, researchers used the Taguchi method to help identify parameters for each process. These methods utilize two-, three-, and mixed-level fractional factorial algorithms.

Using simulation techniques, researchers analyzed six parameters, including glass CTE and thickness, die thickness, overmold thickness, molding compound and dielectric materials. Each parameter has three levels. “From simulation results and Taguchi analysis, critical parameters can be identified for each process in terms of warpage,” Che said in the paper. “Taguchi methods help to identify important parameters for each process. Based on optimized structures and materials, panel warpage can be controlled less than 7mm in each process step for a 550mm X 650mm panel.”

Machine learning fan-out
In a separate paper at ECTC, AMD and the Singapore University of Technology and Design used a machine learning approach to improve the accuracy of warpage simulations.

“While modeling warpage using finite element models is a good way to predict stresses and warpage, the analysis results are only as good as the assumed model inputs such as material properties,” said Cheryl Selvanayagam from the Singapore University of Technology and Design, in the paper. Others contributed to the work.

Instead of this method, researchers used machine learning. Specifically, they used a Bayesian framework incorporating a Markov Chain Monte Carlo algorithm. “This method is a subset of the Bayesian Inference approach where the posterior distribution of the parameter is determined by random sampling of the probabilistic space,” Selvanayagam said.

This approached was combined with FEA simulations, which in turn identified the material parameters that impact warpage. “The proposed technique can enable us to design better packages with locally tailored material properties (by tuning metal layer densities, for example) to enable us to stay within an acceptable warpage threshold,” Selvanayagam said.

Other approaches
Qualcomm also presented a paper at ECTC, where it described a model to analyze the warpage of IC packages.

Qualcomm devised a variation prediction scheme with a numerical model. In the paper, Qualcomm said that molded packages are simulated during the reflow profile. “The effective strain of molding material, consisting of chemical shrinkage and cooling strain at gel point, is calculated and included in the numerical model. By employing different chemical shrinkage strains from different directions, the warpage variation curve was accurately described and simulated by a numerical model,” said Yuling Niu from Qualcomm in a paper at ECTC. Others contributed to the work.