Manufacturing Bits: June 4

Chiplet printer
A number of companies, R&D organizations and universities separately presented a slew of papers and technologies at the recent IEEE Electronic Components and Technology Conference (ECTC) in Las Vegas.

It’s difficult to write about all of the papers at ECTC. But one paper that stood out is a prototype chiplet micro-assembly printer developed by the Palo Alto Research Center (PARC), a unit of Xerox. Still in R&D, the printer handles chiplets from 10μm to 200μm in size. The goal of the printer is to integrate millions of chiplets over large areas for next-generation electronic systems.

In chiplets, the basic idea is that you have a menu of modular chips, or chiplets, in a library. Then, you assemble chiplets in a package and connect them using a die-to-die interconnect scheme.

Developing tiny chips in a fab is difficult. Another challenge is to place each chip or chiplet in an IC package without an error. “Current chip assembly approaches have different limitations. Robotic pick-and-place tools have low throughput and cannot handle small chiplets. Parallel pick-and-place transfer processes such as with contact rubber stamps have fine registration, but need specialized chip fabrication with anchors, is not programmable, cannot perform heterogeneous integration in one step, and does not scale to continuous processes,” said Bradley Rupp, a researcher at PARC, in a paper at ECTC. Others from PARC also contributed to the work.

PARC’s chiplet printer, meanwhile, can handle any type of chip from a foundry. The printer consists of an assembly region, where the chiplets are placed after the fabrication process.

The assembly region, which resembles a small table, is actually an active matrix addressable array. It is similar to the backplane of a display, according to PARC. In the flow, the chiplets are dispersed in a solution. Then, the devices are placed in the assembly region. The assembly region is an electrode array, which generates dynamic electric field patterns.

The dynamic electric field patterns then assemble the chiplets into specific arrangements. The chips are then transferred to a separate substrate using a contact stamping or an electrostatic roller belt. “(The roller belt) consists of an intermediate conductive belt that electrostatically picks up assembled chips row by row under the transfer nip using a non-contact process,” Rupp said.

“There are two system configurations. A 50μm pitch electrode array over a 4cm2 area, which uses up to 200 V actuation patterns, and 10μm pitch electrode array over a 1mm2 area which uses up to 30 V actuation patterns,” he said.

With the technology, PARC and Sandia National Labs have demonstrated 70 chips in an array of 50μm x 200μm. The printer can be used for LED displays, sensor arrays, micro solar arrays, heterogeneous antennas and metamaterials.

Plating power packages
At ECTC, Advanced Semiconductor Engineering (ASE) presented a paper on a new copper plating process for embedded power chip packages.
The technology could pave the way towards more flexible embedded packages for power semiconductors.

ASE described a new plating process for its advanced Embedded Active System Integration (a-EASI) technology, which is a package type for use in DC/DC converter modules, IGBTs, power MOSFETs and others.

The a-EASI package itself combines an embedded die process with a leadframe. Both single and multiple dies can be embedded in an organic laminate material. The electrical contacts to the devices are achieved using laser-drilled and metallized microvias, according to ASE.

In the paper, ASE described a through-hole (TH) filling process using direct-current (DC) electroplating. In plating, the big challenge is to avoid seams or voids in the through-hole or micro-via structures. “With increasing the core thickness for IC substrates, it is extremely difficult for TH to fill without void formation and requires a long plating time,” said Yung-Da Chiu from ASE in the paper. Others from ASE contributed to the work.

To avoid these and other issues, ASE used a specific drilling method and created an x-shape through-hole structure. “For up to a 200μm substrate thickness, the drilled method was changed from mechanical drilling to laser drilling due to advantages such as faster drilling rates and higher quality,” Chiu and others said in the paper.

“The drilled outcome of laser drilling for TH displayed an x-shape formation, which was different from column-shape of mechanical drilling. Fortunately, this geometry characteristic was beneficial for the copper bridge at the TH center, which avoids the void left on the TH and reduces the plating time,” Chiu said.

In addition, organic additives were applied to the structure. This in turn created faster copper deposition at the TH center rather than at the opening. All told, the x-shape through-hole structure with depth of 350μm was filled by DC electroplating within two hours. “This filling ability development enables the embedded chip package design (with) more flexibility,” Chiu added.

Panel fan-out
After years of R&D, panel-level fan-out packaging is finally beginning to ramp up in the market, at least in limited volumes for a few vendors.

In production for several years, today’s fan-out technologies involve packaging a die in a round wafer format in 200mm or 300mm wafer sizes. In panel-level fan-out, though, the package is processed on a large square panel. By increasing the number of die per substrate, a vendor could see huge productivity gains and lower costs over today’s fan-out processes.

Several companies and consortiums are working on the technology.

At ECTC, the Industrial Technology Research Institute (ITRI), National Chiao Tung University, Unimicron and Brewer Science presented a paper on an RDL-first fan-out panel-level packaging process for heterogeneous integration.

Panel-level fan-out has several challenges. “First, the warpage control of a molded panel is a crucial problem for FOWLP technology development,” said Yu-Min Lin from Taiwan’s ITRI. Others contributed to the work. “In this paper, finite element analysis (FEA) is applied to study the influence of back-end-of-the-line (BEOL) process-induced warpage, as well as characterization for simulation, and investigation of each single process.”

In this fan-out panel process flow, a liquid release material is coated onto a 370mm x 470mm glass carrier. “After baking, three layers of redistribution layer (RDL), passivation, and Cu leads are fabricated on the panel with coating, exposing, developing, lithography, and electroplating processes,” Lin said.

Then, 10mm x 10mm test chips with micro solder bumps are thinned down. “Test chips are then flip-chip bonded onto a glass carrier with a pre-bond and reflow process,” Lin said. “After panel molding, a laser debonding method, another key technology advancement, is utilized for panel debond. Debond performance, which is directly related to laser parameter and panel-level package structure, is critical.”

After debonding, the molded panel is cleaned, followed by dicing. “The demonstration of RDL-first PLP technology without interposers proves its great potential in heterogeneous integration applications,” Lin and others added.