Manufacturing Bits: Nov. 17

Intel’s gate-all-around FETs
At the upcoming IEEE International Electron Devices Meeting (IEDM), Intel is expected to present papers on its efforts to develop gate-all-around transistors.

One paper from Intel describes a more conventional gate-all-around transistor technology called a nanosheet FET. Another paper involves a next-generation NMOS-on-PMOS nanoribbon transistor technology. (For a preview, go to the link and then look for paper 20.6, entitled “3-D Self-Aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling,” C.-Y. Huang et al, Intel.)

IEDM will be held as a virtual event from Dec. 12-18.

Nonetheless, finFETs, the current state-of-the-art transistor type, is a tiny 3D-like structure in which the control of the current is accomplished by implementing a gate on each of the three sides of a fin. Today’s finFETs are expected to run out of steam when the fin width goes beyond 5nm.

Then, a new transistor type is required, namely a gate-all-around FET. An evolutionary step from finFETs, gate-all-around transistors provide better performance than finFETs.

Chipmakers are developing one type of gate-all-around technology called a nanosheet FET. Samsung is developing a nanosheet FET for the 3nm node, while TSMC is targeting a similar structure for 2nm. Intel has not publicly announced its plans in the arena.

A nanosheet FET is basically a finFET on its side with a gate wrapped around it. A nanosheet consists of several separate and thin horizontal pieces or sheets, which are vertically stacked. Each sheet makes up a channel.

A gate surrounds each sheet, creating a gate-all-around transistor. In theory, nanosheet FETs provide more performance with less leakage, because the control of the current is accomplished on four sides of the structure.

Then, at 2nm and beyond, the industry is developing a similar structure called a complementary FET (CFET). Nanosheet FETs use different devices for the nFETs and pFETs. In CFETs, though, the nFET and pFET are integrated in the same structure.

Intel refers to this device as a nanoribbon transistor. At IEDM, Intel will describe NMOS-on-PMOS transistors built from multiple self-aligned stacked nanoribbons.

Intel devised a 3D stacked CMOS nanoribbon inverter, which can achieve a 50% area scaling benefit over a 2D device. The width of the nanoribbon is about 13nm, according to Intel. The inter-NR spacing is 9nm with a 50nm spacing between the top NMOS to the bottom PMOS, according to Intel.

“This architecture employs a vertically stacked dual source/drain epitaxial process and a dual metal gate fabrication process, enabling different conductive types of nanoribbons to be built so that threshold voltage adjustments can be made for both top and bottom nanoribbons,” said C.Y. Huang of Intel in an abstract about the technology. Others contributed to the work. “The approach combines excellent electrostatics (subthreshold slope of <75 mV/dec) and DIBL (<30mV/V for gates ≥30nm) with a path to significant cell size reduction due to the self-aligned stacking.”

Vacuum transistors
At IEDM, the Massachusetts Institute of Technology, Harvard and Massachusetts General Hospital will present a paper on a silicon vacuum transistor technology for use in high-frequency and power device applications. (Go to the link and then look for paper 5.2, entitled “Demonstration of a ~40kV Si Vacuum Transistor as a Practical High Frequency and Power Device,” W. Chern et al, MIT.)

Years ago, vacuum devices were commonplace in electronic systems. They are still used in high- voltage applications like satellite, radar and other applications.

But various power devices, such as IGBTs and thyristors, have displaced vacuum electronics. Devices based on silicon carbide (SiC) and gallium nitride (GaN) provide better performance.

Researchers from MIT others have found ways to extend vacuum devices. At IEDM, an MIT-led team will describe a silicon vacuum transistor operating at ~40 kV.

“Such a high voltage level is normally reserved for wide-bandgap materials like SiC and GaN,” according to an IEDM abstract from researchers. “The proof-of-concept device consists of a gated field emission array or FEA (i.e., an electron source), a vacuum drift region and a metal anode. Electrons are emitted from the gated field emission array into the vacuum through tunneling and are collected at the anode. The vacuum determines the transport properties and the high-voltage isolation.”

Vacuum transistors are suitable for a range of high-power and high-frequency applications as well next-generation X-ray sources.

3D ICs
At IDEM, ARM and GlobalFoundries will describe a new 3D IC technology and test vehicle. (Go to the link and then look for paper 15.1, entitled “A High-Density Logic-on-Logic 3DIC Design Using Face-to-Face Hybrid Wafer-Bonding on 12nm FinFET Process,” S. Sinha et al, Arm-GLOBALFOUNDRIES.)

The technology is based on a face-to-face wafer-bonding technology with 5.76µm-pitch 3D connections and 12nm finFET devices.

The technology and its “cache-coherent interconnect mesh (to allow synchronized operations in each layer) operated at up to 2.4GHz, with 10x lower bandwidth density (3.4 TB/s/mm2) and energy usage (0.02 pJ/bit) versus state-of-the-art 2.5D/3D bump-based technologies,” according to the IEDM abstract.