Materials, Software And Techniques

The future of advanced semiconductor technology is about to split evenly into three different areas.

On the leading edge of manufacturing, Applied Materials CEO Mike Splinter called it correctly—it’s all about materials. Just shrinking features isn’t buying much anymore. In fact, at advanced nodes, with extra margin built into designs, it frequently doesn’t buy anything except extra real estate on a semiconductor wafer.

The gains in performance and power—and they’re usually viewed as interchangeable—will come from new materials. STMicroelectronics already showed that with fully depleted silicon on insulator (FD-SOI). Changing out the fins on a finFET with III-V class materials will help, as well. So will graphene and carbon nanotubes and other organic materials.

The big question there is not whether research and engineering know-how can make this all work. It’s how long it will take before processes are mature enough to provide enough economy of scale to warrant moving to these technologies en masse and which ones will emerge as the winners first. There will always be companies experimenting with the latest technologies. That doesn’t mean there will be widespread adoption, though.

The second area of improvement involves architectures—hardware, software, and hardware plus software. Heterogeneous compute structures, stacked die, and improved kernel engineering on software will go a long way toward improving power and performance.

A good example of this is Apple’s new MacBook Air, which provides nearly double the battery life the previous version. At 10 to 12 hours, that’s enough to keep working on a flight from the United States to Asia. The key here isn’t the hardware. It’s the software, which in the past was written with an eye toward functionality rather than performance or power. In the mainstream productivity application world, the software isn’t any faster today than it was a decade ago, and frequently it runs more slowly. New kernel engineering for the software will help. So will giving software engineers the tools to understand how their code interfaces with hardware.

Stacked die with Wide I/O, shorter distances between logic and memory and high-bandwidth memories will add another level of power/performance options. Test chips already are being produced using interposers and TSVs. There is an obvious complementary relationship between logic at the most advanced nodes using the latest technology and materials and standard subsystems, I/O, and analog at older nodes. Faster time to market, more customization options and lower NRE all will push this approach forward at some point, whether it’s one year or five years from now.

That leads to the third development—improvements at mainstream process nodes. Not everything needs to move to the latest process node if there are enough advances at older nodes. This is particularly true for the explosive growth in the Internet of Things, and if stacked die begin gaining traction there will be plenty of opportunity for consistent improvements of certain components at older nodes rather than developing everything for the latest process.

Taken as a whole, this is a very good time to be in the semiconductor industry. There are opportunities for improving performance, power and area on every level, and all options are on the table involving packaging, manufacturing and design—and the integration of all three.