Multi-Die Assemblies Complicate Parasitic Extraction

The shift from planar designs to multi-die assemblies with complex interconnects is transforming what had become almost an afterthought in the design process into a first-order challenge.

Parasitics include things like inductance, capacitance, and resistance, which have become more problematic at advanced nodes due to increasing logic density, thinner interconnects and insulators, and a spike in the amount of data that needs to be processed, moved, and stored. In order to circumvent the size limitations of a reticle, large chipmakers have shifted away from planar SoCs to multi-die assemblies in custom-designed packages. But in doing so, they have added many more interconnects and complex interactions, making it much harder to identify and mitigate parasitic effects.

“Hybrid bond links have brought the die stacks very close to each other,” said Krishnakumar Sundaresan, engineering scientist at Synopsys. “In the past, when people stuck things together with micro-bumps or C4 bumps, etc., it was far apart, and the influence of one die to the other did not exist. With different packaging technologies that are coming up today — like InFo and wafer-on-wafer, and all those different techniques — there has been a significant influence of inter-die coupling, so those need to be extracted. People are now talking about how to get this coupling, and then how to close this block on the die. That is a significant change in the needs of design closure today. People also are thinking about how to comprehend these things upfront in a shift-left strategy, because everybody has a time schedule that needs to be met. Projects are always tight, and things happen in parallel. Therefore, they are also talking about how to comprehend these things early on, so that when they close the die, they can do it upfront.”

Stacking dies adds a whole other challenge. In a 2.5D or 3D-IC design, through-silicon vias might run from the front to the back side of a metal stack, or anything in between. “These elements could be on the interposer to connect the die with the package or a board using micro-bumps, copper pads for hybrid bonding through dielectric vias, or RDL interconnects,” said Dusan Petranovic, technical product management director at Siemens EDA. “All of these need to be modeled, and they all introduce new parasitics. There are also some inter-die interactions between those components, and intra-die interactions — meaning two dies can interact, or a die and interposer, or some kind of organic package. All of that requires a lot of new development. And if you take into account that high frequencies are now used for these interactions, there are a lot of new challenges. Parasitic extraction is a crucial step in design and verification for all chiplet-based systems, and it is essential for maintaining signal integrity, power efficiency, thermal stability, and overall performance.”

In 3D stacks, there are two reasons to extract parasitics. “On the one hand, the parasitics of the connections between the circuits in the stack must be extracted, which a 3D solver can handle well,” according to Andy Heinig, head of Chiplet Center of Excellence at Fraunhaufer IIS/EAS. “However, it becomes challenging when the interconnects of one circuit couple onto the next circuit in the stack due to particularly high frequencies. In that case, the interconnects of both circuits must be analyzed together. To do this, the data of both circuits must be merged, and a joint extraction must be performed. This is very computationally intensive due to the large number of structures involved.”

This is so important particularly in chiplet design because parasitics affect not only the signals themselves but also power integrity. “To ensure power integrity, the entire power/ground network must be extracted. Parasitic extraction is used for this purpose. It allows for accurate analysis of voltage drop and dynamic behavior,” Heinig noted.

These are new twists on familiar problems, but solving them is becoming increasingly complex. “Parasitic extraction tools have been around since the early days of EDA,” said Marc Swinnen, director of product marketing at Ansys. “Parasitics used to be an afterthought. It used to be that you took your devices and modeled them in SPICE, and then you ran SPICE. And what about the wires? The wires need a little bit of resistance/capacitance. It’s a fine-tuning correction just to get a bit more accuracy. But it wasn’t that important. As technology got smaller and smaller, the wires became more and more important in their effects, so the parasitics kept growing and growing.”

Today, device parasitics rival the transistors in the impact they can have on the circuit behavior. “And yet the mindset is still, ‘Oh, it’s just a parasitic,'” Swinnen observed. “It’s not really part of the main flow. It’s this thing we do on the side. But you’re talking about half the behavior of the circuit, which is where people spend most of their time. If you see what engineers spend their time on, it’s debug. They’re not debugging devices. They’re debugging the wires and the parasitics.”

This is no longer just a refinement on top of the basic flow. It has become a key factor in system performance. “What’s changed between now and 5 or 10 years ago? First, there are ever-higher frequencies,” Swinnen said. “As you go to higher frequencies, instead of having one lumped resistance, you need to do much finer distribution of your resistances. The number of these explodes. As the geometries shrink and the frequencies go up, the number of parasitics goes into the thousands, so you need to have a distributed RC of your wire, not just a lumped RC. That means there’s now thousands and thousands of RCs all over your design. The numbers just increased exponentially.”

Chiplet complications
The increasing adoption of chiplets doesn’t help matters. “The interposer, the other chiplets, their power supplies, noise — everything is going to impact a single chiplet,” said Rajat Chaudhry, product management group director for Voltus at Cadence. “So as you go through the maturity aspect of the design, you can then start bringing in the impact of the other chiplets onto a single chiplet. Modeling it all flat becomes challenging, because the elements you need to model become very big. So you may need a hierarchical modeling capability, where you start building models of the remaining chiplets. You design one chiplet, and then you can have a bottom-up and top-down approach. You can have a top-down approach where you see at the board level, at the boundaries of the chiplet, what voltage you’re seeing from the top level. Then, you can divide the problem and model the single chiplet in much more detail and take the boundary voltages from a higher-level simulation, and then model that and do the analysis. This means a chiplet designer would do their analysis with the boundary values from a system-level perspective. That’s the kind of methodology we need going forward, and those are the challenges that are going to be there.”

Getting this correct can affect how a system and its various components behave under different workloads. “The tool needs to capture at the port of each chiplet if the voltage/power supply value is high enough, meeting what is required for the transistors to work and for the cells to perform,” Chaudhry said. “What have you assumed about the power supply at the ports, and what is the drop inside the chiplet? When you take that into account, is that meeting whatever you’re using for your timing margins? In essence, you’re trying to capture that the supply at the ports is where you want it to be, or the assumptions you’re using when you’re doing your design.”

On the chip, it’s relatively straightforward. It’s just resistance and capacitance. “But now the other complexity is longer power supply lines through the interposer and through the package, or there are TSVs or through-dielectric vias (TDVs),” he explained. “In those true 3D stacks, there are multiple kinds of vias that provide the power supply through either the TSVs or TDVs, so you need to have the right models for that. That’s another challenge. There’s an element of getting the system and simulating it, but then you also need to get the parasitic models correct. You need inductance, capacitance, and resistance of these different new types of elements that we did not deal with in the SoC. Then, depending on the kind of heterogeneous system, there are some that may require more electromagnetic kinds of extractors, whereas in the other ones, you can just do simple Manhattan extraction. That’s another thing that we have to determine — what kind of models do we need to build for the different aspects of the system?”

Bigger and badder
Size and density matter when it comes to parasitics.

“When you have a bit larger scale, you need to start modeling it a little differently,” Chaudhry said. “Whereas on-chip, the scales are much smaller. That’s all we were doing for power integrity, and simple RC was good enough. As we get into larger scales, now we need to start looking at inductance and inductive effects.”

Compared to traditional SoCs, it’s a whole different world. “First of all, you have this interconnect that now requires RLC extraction through interposers,” said Siemens’ Petranovic. “Then you have serial communications that are very fast, and which now can go several hundred gigahertz. Then you have parallel buses between HBM for memory and logic processes. This is crucial communication. Typically, they use bridges, which are multiple parallel lines that communicate very fast to have this fast transfer of data between memory and logic and the processor, or whatever logic for processing. Those can go up to 20 gigahertz. Again, if you have this high frequency, you have to consider the high frequency effects and frequency-dependent losses. You have a lot of things to worry about, including the signal integrity, coupling, and mismatches. High frequencies are really introducing a lot of new impacts, and the high frequencies are needed to make efficient systems. Then you have TSVs, and you have to extract those TSVs. Then you have communication. Do you have interactions between different components? You have to extract that interaction. That could be simple capacitive interaction, like coupling capacitor between components as frequencies go higher. It also might be electromagnetic interactions, inductive coupling.”

There are further considerations for multi-die designs, including a future foundry-agnostic approach. “In today’s world, people are talking mostly about a single foundry approach for multi-die, where chips from two different processes from a single foundry are placed on an interposer,” said Synopsys’ Sundaresan. “But in the future, we need to have solutions that are foundry agnostic. This means you can place chiplets from Foundry 1 and Foundry 2 on top of each other and be able to close the design. Then, of course, you have a situation like having different types of design databases and place-and-route GDS to place on top of each other. How do we handle these things? From a tool perspective, we need to have a single, comprehensive interface toward handling these things. That is one big thing that needs to be handled. Extractions are the first place where you will see this complication coming. That is something we should definitely be aware of.”

In addition, chiplets will be developed using different process technologies. “There are different process corners, and how to combine all of this into one system with this number of corners can multiply very quickly,” said Petranovic. “Then you have silicon interposers, organic interposers. You might have a simple parallel Manhattan interconnect with silicon interposer. Or you might have board-like layouts in these organic interposers with the non-mechanical interconnect with special shapes like teardrops and stuff like this. And you have to somehow extract both. In addition to that, you have to model thermal effects and electromigration, because the current density can lead to electromagnetic failures, and thermal introduces variations in resistance. Resistance especially can cause variability. These have to be taken into account. Then, you have power delivery networks that are becoming more complex right now. You have to deliver power to all of these stacked chips.”

When an engineer decides to model something, they first must figure out what is important to model and what level of accuracy is needed. “This can determine what tools are used, so then what models are needed,” Petranovic said. “In chip level extraction, you can use 2.5 D tools/rule-based tools in many cases/ situations, even though there are some fast field solvers used there. But now, when we go to these 3D-ICs, you have this fast communication. You have these frequency-dependent effects that can be only accurately caught. So the question is, what is accuracy? When you decide on the tool, which tool depends on what accuracy? Yes, those could be kept with the full wave solvers, but full wave solvers cannot deal with complexity, performance, integration, flow. So we have the dilemma of how much to extend the existing tools, and how to immediately bring the most accurate tool. And if you bring the most accurate tools, how do you integrate them, make them perform better, and handle the complexity that this needs?”

Physical effects
As frequency goes up and process nodes go down, there are additional effects that come into play.

“One of the obvious effects is inductance,” Ansys’ Swinnen said. “Inductance is a bit of a game changer, but there are other multi-physics effects to consider, including thermal effects, which can change the resistance. Also, at advanced nodes, things like layout-dependent effects (LDE) must be considered, which is the behavior that your wire or your transistor depends on, not only of its own characteristics, but also what is placed around it. And so the placement of other elements near your element changes how it behaves, and those are called layout-dependent effects. These are all the reasons why parasitic extraction has become more difficult, more multi-physics, and more important.”

In multi-die/chiplet and 3D-IC designs, all of this just gets compounded, because not only are we concerned about the individual chiplet, but the relationship within the chiplet system or between die stacks.

“When you have a multi-die, the only reason that we can tolerate this disaggregation and not suffer from a huge impact on power and performance is that we put the chips really close together and have them communicate at very high bandwidth and very high speeds with each other,” Swinnen explained. “Then you can simulate being on one chip, and don’t pay a huge penalty for disaggregation. But that means you have these very high-speed communication channels between the chips, like UCIe, for example, and they have these SerDes and PHYs that are very, very high frequency, and you can’t extract those with just an RC. There, you need a full RLC. Also, you need a full electromagnetic analysis. Now, RLCG comes into play, where G is the conductance. It’s resistance, inductance, capacitance, and then the reverse of resistance, which is the conductance, and that’s been around forever. RF designers have always had to deal with this, but RF was like a niche in the design market. Now every digital design of every AI chip has to deal with RLC and electromagnetics, so it’s new for them. Even the vertical connections, like the TSVs, need an RLC model.”

What’s significant about multi-die design is that the interposer is typically passive, so it connects an active chip to another active chip. “The extraction of the interposer is just the passive part, and there’s a bit more passive to get through the chips, and you need to extract the entire path, and that means you need a multi-die view,” Swinnen said.

Conclusion
“When you have a single die, the amount of effort the person who’s closing the die invests on figuring out whether the thermal intensity of the chip is fine,” said Vamsi Thatha, product manager for parasitic extraction at Synopsys. “Was there any electromagnetic interference or is the power distribution across the design? Fine. But the amount of attention that goes into these things when you are working on a monolithic die versus when you switch to multi-die or stacked die is exponentially different. Look at the interposer, where you put multiple die on it. Something will have to take out all the heat coming from all these chips. You have glass substrates over there, interposer over here. There is a way for the heat to escape. But when you go to stacked die, the heat cannot escape. There is no way it comes out. Now, the question goes back to how would somebody figure that out during extraction? Another way to ask is, ‘There are so many nets that are wide metal going on top of each other from two different wires. Is there going to be any magnetic interference? There are certain methodologies in the extraction world to extract your inductance of the net. Then people will go run the electromagnetic inference tests to figure out if there was any magnetic interaction between these two chips. All of these were part of the extraction world.”

At the end of the day, it comes down to fundamentals. “Within the monolithic world, there are flows for thermal air extraction,” Thatha said. “There are flows where you can extract inductance, and there are specific questions for the power grid extraction. With all of these, the difficulty of the context increases when you move to stacked die. Today, every flow that we have in the monolithic side, from the basic temperature sensitivity flows all the way to the thermal-aware, and all the electromagnetic flows need to be ported to the stacked die. So now the question is, who is signing off on all these? Are you sure your design is PI and SI safe? Then, did you make sure there are no electromagnetic inference issues observed in the design? Is the power distribution good? Did you run any sort of thermal analysis? Those are the basic questions that we put to the person who’s signing off on the model.”

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