NAND ATE Market Gets Testy

Ensuring quality requires more test coverage, which increases time and maybe cost.

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The NAND flash memory market is undergoing big changes. As planar NAND moves further down the 1xnm node regime, suppliers are ramping up devices with new cell structures, interfaces and other features. And on top of that, 3D NAND is beginning to appear in the market.

The next-generation NAND devices will enable new applications in the mobile and enterprise markets, but the chips themselves present some manufacturing challenges for memory vendors. One of the obvious challenges is that vendors must ensure the quality of the devices. What isn’t so obvious is that vendors may need to bolster their test floors.

In fact, the new wave of NAND devices will require more test coverage than previous chips. This, in turn, could boost test times and possibly costs. So, for suppliers of automatic test equipment (ATE), the challenge is to develop testers that can not only address leading-edge NAND devices, but also keep the test times, and the overall cost of test, in check.

“Flash is a low-cost, high-volume market,” said Ken Hanh Lai, product marketing manager at Advantest America, the U.S. subsidiary of ATE giant Advantest. “For NAND testing, we are under even greater pressure to reduce test costs for customers. Our customers need to keep their test costs low, but they must also be able to maintain the quality and reliability for their devices. So, I believe more testing would be necessary to do that.”

The need for more stringent testing is becoming apparent on several fronts. “The usage model is changing,” Lai said. “For example, the (add-on) card market was consuming much of the NAND capacity. But if a card was broken, you just returned it and bought a new one. The card market still exits, but it’s slowly transitioning to the embedded market. They are built-in to the device. The problem is that if something goes wrong, the whole device gets returned.”

All told, ATE vendors, and their customers, face a number of challenges in NAND. “They have to stay ahead of the curve,” said Mark Stromberg, an analyst with Gartner. “The test times have been increasing, particularly for NAND test. With regards to the read and re-writeability of the device, that’s a big issue, especially as you start looking at some of the new products that are using NAND, such as SSDs.”

In response, ATE vendors have rolled out a new class of testers or capabilities to address next-generation devices. The question is whether chipmakers are willing to pay for new ATE. Some may opt to extend their current ATE, which may have some consequences in terms of test times. “Chipmakers really try and cut costs in test—and for a simple reason,” Stromberg said. “Test is more of a verification process that ensures your part works. It’s not really viewed as a value-add per se. You are not adding functionality to die.”

Testy market
The ATE market for NAND is a bright spot in an otherwise tumultuous business. There were more than a dozen ATE vendors in the 1980s, but the market has experienced a dramatic shakeout over the years. Today, in fact, the industry consists of only three major ATE players in logic—Advantest, LTX-Credence and Teradyne.

Advantest and Teradyne are the big memory ATE vendors. In addition, there are several small ATE vendors, some of which are giving their larger rivals fits. For example, UniTest, a Korean memory ATE supplier, is basically backed by Samsung. “UniTest is more of a captive shop for Samsung,” Stromberg said. “(Advantest and Teradyne) still sell to Samsung. What UniTest gives Samsung is a little more leverage in terms of tester selling prices and so forth.”

Overall, the ATE industry is a mixed bag. 2013 was a down year for ATE, but the business is expected to rebound and grow by 15% in 2014, according to Gartner. “We feel that there should be some pent up demand coming on stream throughout 2014,” Stromberg said. “One of the big caveats is that we are somewhat worried what may happen on a macroeconomic basis. If there is any sort of a slowdown in end-user demand, the OSATs, in particular, will really start holding off on capital orders.”

Digital is the largest ATE market. “In SoC test, the 2013 market fell to $1.9 billion, lower than the general market forecast of $2.3 billion at the beginning of the year,” said Mark Jagiela, president of Teradyne, in a recent conference call. “While 2013 illustrates the difficulty of predicting the market size this early in the year, we do believe that there will be a rebound in the digital segment and the market will likely be in the $2.1 billion to $2.4 billion range.”

In comparison, memory ATE was a $2 billion business about 10 years ago. But following a massive shakeout in the DRAM and flash markets, the memory ATE market has dwindled. Last year, the total memory ATE market was just over a $400 million business, according to Gartner.

Still, the memory ATE market is projected to jump by 16% in 2014, according to the firm. “A lot of the capital budgets in ATE are concentrated on the flash side,” Stromberg said. “Most of the NAND testing at this point is done by the IDMs and they are a little more rigid with their capital budgets. It doesn’t mean they would push some of this out, but they don’t move their capital budgets as aggressively as the OSATs do.”

In total, the NAND flash market itself is projected to hit $32 billion in 2014, up 18% over 2013, according to RBC Capital Markets. Bit growth is expected to jump 40%, while capital spending is projected to grow by 18%, according to the firm.

NAND test challenges
NAND is also going in several directions. On the process front, planar NAND is slowing and expected to hit the wall at 10nm. So, vendors are developing next-generation 3D NAND. In addition, the planar devices themselves can be single-level cell (SLC), 2-bit multi-level cell (MLC) or 3-bit MLC. Plus, there are traditional NAND and DDR NAND. And there are two competing interfaces — Toggle Mode and ONFI.

The diversity presents some challenges for test engineers. “You have to characterize the heck out of the parts,” said Jim Handy, an analyst with Objective Analysis. “With today’s NAND, a wide array of parameters can be set internally. Because there is such a wide range, finding the right mix can take a very long time. But the chip has to ship to make money. So the time pressures on the engineers are enormous.”

Time to market is one thing. Ensuring the quality and reliability of today’s devices is another. “You will really need a more capable tester to be able to test these devices,” said Advantest’s Lai.

Responding to the demands in NAND, Advantest, Teradyne and others have recently rolled out new testers or capabilities. These systems are either general-purpose or dedicated testers. “If you build a general-purpose tester, this tester would need to test all of the memory out there,” Lai said. “For this type of tester, you would be spending a lot of money.”

The big ATE players tend to offer dedicated memory testers, which can still test a range of different devices. Advantest’s new NAND ATE system, dubbed the T5831, is based on a tester-per-site architecture. The system provides site-chain support and concurrent test. It also supports bad block management capabilities, ECC grading, among other features.

Despite the new ATE, next-generation NAND devices may still require more test coverage, thereby boosting test times. “You have some devices that require short test times and some with longer test times,” Lai said. “Test times increase because the die density increases. To some degree, they track each other. You have more memory bits to test. So therefore, your test time will obviously increase.”

Test engineers must deal with several other issues as well. For example, the speeds and complexity of the memory cells are also increasing. “NAND, right now, is operating at about 400-megabits per second. In the future, people are talking about 500-megabits per second and into 800-megabits per second in the future,” he said.

“And as things get more complicated and the number of bits increase, they are finding problems with the cells,” he said. “For example, you have flash cells that hold three bits per cell. At three bits, it’s basically eight different threshold levels within the same voltage range you used to have. As you cross from one voltage threshold into another, you are basically changing the content of the flash cell. You are talking maybe like a couple hundred millivolts between thresholds. And how do you test the device in such a way that the device would be able to distinguish from one threshold to another? And how would you calibrate the device? It requires a lot of calibration of the device itself and that’s where the tester helps.”

Another challenge is to test NAND in mobile systems. In smartphones and other mobile products, NAND, DRAM and other devices are being stacked and sold in the form of multi-chip packages (MCPs). Today’s MCPs could have as many as 16 dies in the same package.

Testing all the bits in a package requires long test times. One way to cut test times is to perform concurrent testing of all dies in a package. “People can either adopt a two-pass technology, where they can test one flash device first and then test the DRAM second. Or they test both devices concurrently in the same package, meaning that there are two test programs running and testing the device at the same time. That basically demands a different test architecture,” Lai said.

“In the classical tester architecture, you typically have a fixed number of I/O pins and a fixed number of PPS channels,” he said. “In the new system, we have the capability to assign more or less PPS channels per device as needed by the customer.”

All told, testers must support at-speed testing up to 800 megabits-per-second at 10% margin with an overall timing accuracy of <200ps. “It must also be capable of LPDDR2 DRAM types of speeds, up to 1.2-gigabits-per-second as well. This is where we have the capability to do MCP test, in which we can test both flash and DRAM at the same time,” he said. In any case, the bad news for ATE and other equipment vendors is that the smartphone market is slowing. The good news is that there are other drivers in the NAND arena. “Bit growth is still pretty good,” Lai said. “The ASPs are stabilizing. The driver is still basically the mobile market, but there is strong demand for SSDs.”