Maximizing performance and minimizing costs require collaboration across the semiconductor industry.
In the past, integrated circuits, packages and boards were all designed independently, and yet in most cases still managed to fit together with very few functional or technical problems. However, recent advances in chip performance have changed this process dramatically.
New designs, processes and materials already have been seen in packaging as high-performance semiconductor chips need to carefully match the size, power and performance requirements of more demanding end applications. For optimal system performance, specific information related to material, speed and stability has created the need to improve information exchange and collaboration for successful board design. While collaboration is not new to the industry, we are now at a point where collaboration needs to be extended to all parts of the electronic ecosystem in order to maximize system performance while minimizing costs.
Designers across the electronics ecosystem must come to the table to address issues such as:
• Parasitic capacitance and inductance issues that impact signal integrity;
• Board material characteristics to deal with varying frequencies, especially high frequency;
• New package form factors such as thinner packages and 2.5D and 3D packages;
• Packages with tight interconnect spacing creating board design issues;
• Board layout techniques to avoid cross talk, EMI, and short circuits;
• Shorter design cycles with added cost pressure; and
• Designing boards for maximum power reduction and heat dissipation.
On Oct. 13, Semico is hosting a one-day event at the Computer History Museum in Mountain View, Boards, Chips and Packaging: Designing to Maximize Results. This ‘must-attend’ event is bringing together all of the players within the ecosystem to better understand the issues and offer solutions to some of the system degradations or failures that are seen once chips are integrated into packages and then onto boards. This event will feature several keynotes from leading industry experts. Two thought-provoking panels will discuss critical factors for the success system implementation with minimal rework to hit your market price points at the right performance level and within the target market window.
Capt. Chesley B. “Sully” Sullenberger, III will be the guest luncheon keynote and will discuss safety and electronic systems as they relate to high-performance aviation electronics. For more information go to www.semico.com.
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