Securing Smart Connected Homes With OTP NVM IP


The market for piracy is huge and hackers have become increasingly sophisticated even when security is implemented in hardware. The race between the aggressors and protectors is a battle without end. Smart connected home devices are increasingly storing and processing very sensitive and private user data in addition to attempting to deliver copyright protected content from service providers. Pr... » read more

Blog Review: Feb. 5


Cadence's Paul McLellan checks out the different ways persistent memories can be used, as well as a basic persistent programming model and key things hardware needs to support. In a video, Mentor's Colin Walls explains what's different about operating systems for embedded applications and how to go about selecting one. Synopsys' Taylor Armerding finds troubling vulnerabilities in U.S. cri... » read more

New Parasitic Extraction Requirements In Custom Design For The Next Wave Of SoCs


Fast growing markets like 5G, biotechnology, AI, and automotive are driving the new wave in semiconductor design and the need for highly integrated system on chip (SoCs). Power management, sensors, RF and precision analog functionality are all integrated on the same substrate which poses new challenges for custom design tools. Specifically, there are new challenges for parasitic extraction that... » read more

Making Sure RISC-V Designs Work As Expected


The RISC-V instruction set architecture is attracting attention across a wide swath of markets, but making sure devices based on the RISC-V ISA work as expected is proving as hard, if not harder, than other commercially available ISA-based chips. The general consensus is that open source lacks the safety net of commercially available IP and tools. Characterization tends to be generalized, ra... » read more

Aligning Automotive Safety Requirements Between IP And SoCs


Today’s SoCs for automotive safety-related systems integrate numerous IP blocks. At the system level, the Hardware Software Interface (HSI) between these IP blocks needs to be verified in simulation and validated in prototype. However, the scaling of the scope and effort to verify or validate is not linear based on the growing complexity of SoCs and their components such as IP. Depending on t... » read more

Blog Review: Jan. 29


Mentor's Shivani Joshi introduces the basics of PCB layout and the importance of being familiar with a manufacturer's specs. Cadence's Paul McLellan takes a look at why Design Technology Co-Optimization is increasingly necessary as 3nm approaches and new transistor types like CFET and gate-all-around are on the horizon. Synopsys' Sai Karthik Madabhushi recounts an alarming incident that h... » read more

Tradeoffs In Embedded Vision SoCs


Gordon Cooper, product marketing manager for embedded vision processors at Synopsys, talks with Semiconductor Engineering about the need for more performance in these devices, how that impacts power, and what can be done to optimize both prior to manufacturing. » read more

Week In Review: Design, Low Power


Xilinx filed a patent infringement countersuit against Analog Devices, alleging infringement of eight U.S. patents including technologies involving serializers/deserializers (SerDes), high-speed ADCs and DACs, as well as mixed-signal devices targeting 5G and other markets. The counterclaims are in response to Analog Devices' December lawsuit alleging unauthorized use by Xilinx of eight ADI pate... » read more

Week In Review: IoT, Security, Autos


AI/Edge Vastai Technologies is using Arteris IP’s FlexNoC Interconnect IP and AI Package for its Artificial Intelligence Chips for artificial intelligence and computer vision systems-on-chip (SoCs). Startup Vastai Technologies was founded in December 2018, designs ASICs and software platforms for computer vision and AI applications, such as smart city, smart surveillance, smart education, ac... » read more

Dealing With ECOs In Complex Designs


Namsuk Oh, R&D principal engineer at Synopsys, talks about the impact of more corners and engineering change orders, how that needs to be addressed in the flow to close timing, and how dependencies can complicate any changes that are required. » read more

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