tag: Cadence

Tech Talk: Faster Simulation
By Ann Mutschler - 22 Mar, 2018 - Comments: 0

Cadence’s Adam Sherer talks about how to speed up simulation in complex multi-core designs. https://youtu.be/lDgMwU5KN7U » read more

Blog Review: Mar. 21
By Jesse Allen - 21 Mar, 2018 - Comments: 0

Mentor's Colin Walls shares five more quick tips for embedded software programming, including t real time systems, programming philosophy, and C++ operator overloading. Cadence's Paul McLellan digs into recently released semiconductor company ratings, the role of memory in shaking up the list, and China's plans for more 3D NAND and DRAM fabs. Synopsys' Taylor Armerding examines the latest... » read more

Blog Review: Mar. 14
By Jesse Allen - 14 Mar, 2018 - Comments: 0

Cadence's Meera Collier considers the issues of bias implementation in algorithms and AI systems, and whether immense training sets can really solve the problem. Mentor's Cristian Filip digs into the evolution of signal integrity analysis methods and why different data rates require different solutions. Synopsys' Naveen G explains key features introduced in the latest generation of interc... » read more

LiDAR Goes Back To The Future
By Jeff Dorsch - 12 Mar, 2018 - Comments: 0

LiDAR is emerging as an increasingly important piece of the enabling technology in autonomous driving, along with advanced computer vision and radar sensor chips. But LiDAR systems also are finding their way into a variety of other applications, such as industrial automation, including robotics, and unmanned aerial vehicles. Advanced mapping is another rapidly growing market for LiDAR, which... » read more

Why All Nodes Won’t Work
By Ed Sperling - 08 Mar, 2018 - Comments: 4

A flood of new nodes, half-nodes and every number in between is creating confusion among chipmakers. While most say it's good to have choices, it's not clear which or how many of those choices are actually good. At issue is which [getkc id="43" kc_name="IP"] will be available for those nodes, how that IP will differ from other nodes in terms of power, performance, area and sensitivity to a v... » read more

IP And Power
By Brian Bailey - 08 Mar, 2018 - Comments: 0

[getkc id="108" kc_name="Power"] is quickly becoming a major differentiator for products, regardless of whether they are connected to a wall outlet or dependent on a battery. At the same time, increasing amounts of a chips content comes from third-party [getkc id="43" kc_name="IP"]. So how do system designers ensure that the complete system has an optimal power profile, and what can they do to ... » read more

By the Power Vested in Me, I Now Pronounce You (The SoC Designer)…
By Dave Stratman - 08 Mar, 2018 - Comments: 0

…Doomed. Well, maybe that’s a little harsh, but your job won’t be getting any easier; that “happily ever after” may be harder to achieve than you think, and there are a number of reasons why. And by “me” (of vested power), here I’m really talking about the power of the consumer market as a whole and our collective insatiable demand for newer, shinier…well, just plain “coo... » read more

New Issues In Advanced Packaging
By Ann Mutschler - 08 Mar, 2018 - Comments: 1

Advanced packaging is gaining in popularity as the cost and complexity of integrating everything onto a planar SoC becomes more difficult and costly at each new node, but ensuring that these packaged die function properly and yield sufficiently isn't so simple. There are a number of factors that are tilting more of the the semiconductor industry toward advanced [getkc id="27" kc_name="packag... » read more

Meeting The Challenges Of The 2018 National Defense Strategy
By Cadence - 07 Mar, 2018 - Comments: 0

In Secretary of Defense James Mattis’ Summary of the 2018 National Defense Strategy: Sharpening the American Military’s Competitive Edge, he provides a critical framework for driving “urgent change at significant scale.” This paper describes the role that Cadence can play in assisting the nation and its partners in achieving that urgency and scale of change called for in the vision and ... » read more

Blog Review: Mar. 7
By Jesse Allen - 07 Mar, 2018 - Comments: 0

Synopsys' Amit Paunikar and Shaily Khare take a look at new features in LPDDR5, from improved data bandwidth and Deep Sleep Mode to WCK clock. Cadence's Paul McLellan dives into forward error correction, a technique for automatically correcting errors in transmitted network data, with a look at why it's important and how it works. In his latest embedded software video, Mentor's Colin Wall... » read more

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