tag: Cadence

5 Pitfalls That May Kill The IoT
By Frank Schirrmeister - 30 Nov, 2017 - Comments: 0

A couple of weeks ago I participated in a panel titled “The Road to a Trillion Devices” organized by Brian Fuller at Arm TechCon. His closing question was whether we will get to the projected trillion devices in twenty years. My answer was that we may even get there faster. His opening question was what the pitfalls would be to make it difficult to get to trillion devices in the next twenty... » read more

Prototyping Partitioning Problems
By Ann Mutschler - 30 Nov, 2017 - Comments: 0

Gaps are widening in the prototyping of large, complex chips because the speed and capacity of the FPGA is not keeping pace with rapid rollout pace of advanced ASICs. This is a new twist for a well-established market. Indeed, prototyping with FPGAs is as old as the [gettech id="31071" t_name="FPGAs"] themselves. Even before they were called FPGAs, logic accelerators or LCAs (logic cell ar... » read more

Tech Talk: Verification
By Ed Sperling - 30 Nov, 2017 - Comments: 0

Frank Schirrmeister, Cadence's senior group director for verification platforms, talks about what's changing in verification with 5G, machine learning, greater connectivity, advanced packaging, and the growing need to build security into designs. https://youtu.be/GMF8BkmdJzE » read more

Could Liquid IP Lead To Better Chips?
By Brian Bailey - 30 Nov, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the benefits that could come from making IP available as abstract blocks instead of RTL implementations with Mark Johnstone, technical director for Electronic Design Automation for [getentity id="22499" e_name="NXP"] Semiconductor; [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; Bryan Bowyer, director of ... » read more

Three Things You Need To Know To Use The Accellera PSS
By Cadence - 29 Nov, 2017 - Comments: 0

Three primary considerations for adopting the Accellera Portable Stimulus Standard (PSS) are understanding the following: the value and relevance of this standard; the fundamental concepts of PSS modeling, including building blocks, process, and mindset; and PSS portability and how these scenarios can be applied to a specific platform. In this paper, we explore these three topics. To read mo... » read more

Week In Review: Design
By Linda Christensen - 22 Nov, 2017 - Comments: 0

Acquisitions Marvell signed a definitive agreement to buy Cavium for roughly $6 billion. The deal is expected to close in mid-2018. The Cavium deal fits squarely on the cloud side and gives Marvell a much bigger reach into enterprise networking and infrastructure, as well as some developing markets. Siemens paid an undisclosed price to buy Solido Design Automation, which tracks variation i... » read more

Blog Review: Nov. 22
By Ed Sperling - 22 Nov, 2017 - Comments: 0

ARM's Jem Davies talks about an upcoming documentary on AI and where the lines need to be drawn between machine intelligence and human emotional intelligence. Mentor's Saunder Peng examines the impact of merging physical verification databases, which can cost time and resources, and how that can be streamlined. Cadence's Paul McClellan takes a look back at the Xerox Alto and how it change... » read more

Deals: Mentor-Solido, Marvell-Cavium
By Ed Sperling - 20 Nov, 2017 - Comments: 0

Marvell today signed a definitive agreement to buy Cavium for roughly $6 billion, ending weeks of speculation about whether the deal would go through. And Mentor, a Siemens business, paid an undisclosed price to buy Solido Design Automation, which tracks variation in complex designs. Both deals are part of a new flurry of M&A activity across the semiconductor industry as the industry ret... » read more

Move Data Or Process In Place? (Part 2)
By Brian Bailey - 20 Nov, 2017 - Comments: 0

Chip architectures, and even local system architectures, long have found that the best way to improve total system performance and power consumption is to move memory as close to processors as possible. This has led to cache architectures and memories that are tuned for those architectures, as discussed in part 1 of this article. But there are several tacit assumptions made in these architectur... » read more

Blog Review: Nov. 15
By Jesse Allen - 15 Nov, 2017 - Comments: 0

Cadence's Paul McLellan shares highlights from the Jasper User Group, including what to do when formal is not converging on a proof and formal in use at Arm. Synopsys' Anders Nordstrom explains how formal can verify SoC interconnects and get you from San Jose to Austin. Mentor's Jeff Miller argues that intelligent sensors are the basic building block for the IoT, and the market is growing... » read more

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