tag: Cadence

One Belt, One Road
By Ed Sperling - 24 Aug, 2017 - Comments: 0

China's so-called One Belt, One Road policy on global trade could have significant repercussions on semiconductors and IP if it succeeds. It's hardly a slam-dunk, and China has been vying for a larger position in the semiconductor industry for some time. But this is a completely different strategy because China is not attempting to go it alone this time. China has been rather quietly build... » read more

Portable Stimulus Status Report
By Brian Bailey - 24 Aug, 2017 - Comments: 0

The first release of the Portable Stimulus (PS) standard is slated for early next year. If it lives up to its promise, it could be the first new language and abstraction for verification in two decades. [getentity id="22028" e_name="Accellera"] uncorked the PS Early Adopter release at the Design Automation Conference (DAC) in June. The standard has been more than two years in the making by t... » read more

Design And Verification For An Era Of A Trillion Devices
By Frank Schirrmeister - 24 Aug, 2017 - Comments: 0

Scared or excited? When I did a back-of-the-envelope calculation whether the one trillion devices that Softbank’s CEO Masa-san predicted least year at ARM TechCon was possible, I realized that a trillion may be the low end of the range. For me, the geeky excitement about the potential technological progress and how to architect the Internet of Things (IoT) gets balanced very fast with concern... » read more

When Is Verification Complete?
By Ann Mutschler - 24 Aug, 2017 - Comments: 0

Deciding when verification is done is becoming a much more difficult decision, prompting verification teams to increasingly rely on metrics rather than just the tests listed in the verification plan. This trend has been underway for the past couple of process nodes, but it takes time to spot trends and determine whether they are real or just aberrations. The Wilson Research Group conducts a ... » read more

Blog Review: Aug. 23
By Jesse Allen - 23 Aug, 2017 - Comments: 0

Cadence's Madhavi Rao asks whether India should have more fabs and the role government policy should play. Synopsys' Kapil Rajpal checks out the Serial Peripheral Interface, which is emerging as a popular choice in automotive applications, and various vendor specific flavors. In a video, Mentor's Colin Walls explains inter-task communication and the basic mechanisms of how to pass data fr... » read more

IP Biz Changes As Markets Fragment
By Ed Sperling - 22 Aug, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss IP protection, tracking and reuse with Srinath Anantharaman, CEO of [getentity id="22203" e_name="ClioSoft"]; Jeff Galloway, CTO of Silicon Creations; Marc Greenberg, group director of product marketing for [getentity id="22032" e_name="Cadence"]'s IP Group; and John Koeter, vice president of marketing for [getentity id="22035" e_name="Synopsys"]' S... » read more

Blog Review: Aug. 16
By Jesse Allen - 16 Aug, 2017 - Comments: 0

Cadence's Paul McLellan checks out how Imec sees the future of transistors and the challenges of 3D logic. Synopsys' Robert Vamosi gets a lesson on the electronic systems powering modern cars, and considers when it's ethical to hack one. Mentor's Colin Walls takes a look at how to pass data between RTOS tasks. Rambus' Aharon Etengoff looks at recent semi market predictions, from expand... » read more

How Reliable Are FinFETs?
By Ann Mutschler - 16 Aug, 2017 - Comments: 1

Stringent safety requirements in the automotive and industrial sectors are forcing chipmakers to re-examine a number of factors that can impact reliability over the lifespan of a device. Many of these concerns are not new. Electrical overstress (EOS), electrostatic discharge (ESD) and [getkc id="160" kc_name="electromigration"] (EM) are well understood, and have been addressed by EDA tools f... » read more

The Week In Review: Design
By Jesse Allen - 11 Aug, 2017 - Comments: 0

M&A Mentor acquired Valydate, provider of the VERA schematic integrity analysis tool. Founded in 2010, the Canadian company also offered signal and power integrity and static timing analysis services. Valydate's technology will be integrated with Mentor's Xpedition PCB design flow, though former Valydate CEO Michael Alam says it will continue to serve all EDA environments. Tools Aldec ... » read more

Using CNNs To Speed Up Systems
By Ann Mutschler - 10 Aug, 2017 - Comments: 0

Convolutional neural networks (CNNs) are becoming one of the key differentiators in system performance, reversing a decades-old trend that equated speed with processor clock frequencies, the number of transistors, and the instruction set architecture. Even with today's smartphones and PCs, it's difficult for users to differentiate between processors with 6, 8 or 16 cores. But as the amount o... » read more

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