A new technical paper titled “Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width” was published by researchers at POSTECH.
Abstract
“In nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. In contrast, forksheet FETs (FSFETs) enable aggressive CH reduction by introducing a dielectric wall between N/P-type devices. However, FSFETs have inherent drawbacks: one side of the channel and source/drain (S/D) inevitably interfaces with the wall, leading to a compromised electrical performance compared with that of NSFETs. Moreover, when the gate edge aligns with the wall on one side, sufficient GE and GC margins are still required on the opposite side. To address these challenges, we propose patterned multi-wall NSFETs (MW-NSFETs) comprising patterned walls on both sides of the channel, which facilitate gate-all-around channel formation and wrap-around contact, resulting in superior DC behavior. Furthermore, CH can be scaled down as both sides of the gate edges self-align with the patterned multiwall. Consequently, MW-NSFETs yield a higher Ion (4.65%) and lower RC delay (6.2%) at a 12.04% smaller CH than FSFETs. Moreover, at the circuit level, the MW-NSFETs exhibited a higher oscillation frequency compared with FSFETs. Thus, MW-NSFETs represent viable devices for sub-2-nm nodes, meeting the stringent criteria for high performance and minimal CH values in logic applications.”
Find the technical paper here. June 2025.
S. Lee et al., “Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width,” in IEEE Access, vol. 13, pp. 99355-99365, 2025, doi: 10.1109/ACCESS.2025.3576265.
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