Carrier Mapping in Sub-2nm Node NSFETs with SSRM (imec, KU Leuven)


Researchers from imec and KU Leuven published "Carrier Mapping in Sub-2nm Node Nanosheet Transistors with Scanning Spreading Resistance Microscopy." Abstract "As the semiconductor industry transitions to gate-all-around architectures such as Nanosheet-FETs (NSFETs) for the 2nm node and beyond, controlling parasitic resistance through precise junction engineering is fundamental. This requi... » read more

On-Current Performance of Ultra-Scaled NSFETs With Source/Drain Underlap Doping (Global TCAD Solutions, TU Wien)


A new technical paper titled "On-Current Degradation in Ultra-Scaled Nanosheet FETs with S/D Underlap Doping" was published by researchers at Global TCAD Solutions GmbH and TU Wien. Abstract: "Aggressive gate pitch scaling makes it increasingly challenging to control the doping gradient at the source/drain (S/D) extensions. To address this, S/D underlap doping has been proposed as a solutio... » read more

Modulation of the Inner Gate Length in MFMIS NSFETs To Achieve Big Gains in Memory Window (Samsung, Seoul National Univ.)


A new technical paper titled "Inner Gate Length Modulation of MFMIS Nanosheet FET Memory for Advanced Technology Nodes" was published by researchers at Samsung and Seoul National University. Abstract "This work proposes a new way of lowering the area ratio (AR) between the ferroelectric and metal-oxide-semiconductor (MOS) regions of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) ... » read more

Patterned MW-NSFETs For Sustainable Scaling (POSTECH)


A new technical paper titled "Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width" was published by researchers at POSTECH. Abstract "In nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. ... » read more

Simulation Study Of Vertically Stacked 2D NSFETs


A new technical paper titled "Simulation of Vertically Stacked 2-D Nanosheet FETs" was published by researchers at Università di Pisa and TU Wien. Abstract "We present a simulation study of vertically stacked 2-D nanosheet field-effect transistors (NSFETs). The aim of this investigation is to assess the performance and potential of FinFET alternatives, i.e., gate-all-around (GAA) nanosheet... » read more