Patterned MW-NSFETs For Sustainable Scaling (POSTECH)


A new technical paper titled "Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width" was published by researchers at POSTECH. Abstract "In nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. ... » read more

Challenges In Managing Chiplet Resources


Managing chiplet resources is emerging as a significant and multi-faceted challenge as chiplets expand beyond the proprietary designs of large chipmakers and interact with other elements in a package or system. Poor resource management in chiplets adds an entirely new dimension to the usual power, performance, and area tradeoffs. It can lead to performance bottlenecks, because as chiplets co... » read more

Higher Density, More Data Create New Bottlenecks In AI Chips


Data movement is becoming a bigger problem at advanced nodes and in advanced packaging due to denser circuitry, more physical effects that can affect the integrity of signals or the devices themselves, and a significant increase in data from AI and machine learning. Just shrinking features in a design is no longer sufficient, given the scaling mismatch between SRAM-based L1 cache and digital... » read more

Are You Leaving Performance On The Table? Here Is One Sure Way To Find Out


Compute platforms are always hungry for more performance. This is a fact that we simply cannot escape. Whether you are targeting high performance computing, IoT, mobile, or the automotive market, you need to unlock the best performance for your specific workloads. This relentless quest for performance comes with an unwelcome side effect: system complexity. As hardware becomes more capable, the ... » read more