Power Delivery Challenges For AI Chips

As artificial intelligence (AI) workloads grow larger and more complex, the various processing elements being developed to process all that data are demanding unprecedented levels of power. But delivering this power efficiently and reliably, without degrading signal integrity or introducing thermal bottlenecks, has created some of the toughest design and manufacturing challenges in semiconductor history.

Unlike general-purpose processors, chips designed specifically for AI workloads push densities to extreme levels. They pack more transistors into smaller footprints, while also increasing the total number of transistors, usually in the form of chiplets. The result is larger and denser systems-in-package, in which power delivery becomes not just an electrical problem, but a packaging, materials, and systems integration challenge that stretches from the individual chiplets to the server rack.

“Power is largely dominated by dynamic power, driven significantly by data movement between compute and memory,” said Godwin Maben, a Synopsys fellow. “For instance, NVIDIA’s Blackwell ranges from 700 watts to 1,400 watts. That makes efficient bus architectures and architectural innovations, such as data compression strategies, critical.”

Dynamic power dominates due to the sheer volume of data being shuttled back and forth between memory and compute units. These transfers occur across massive memory hierarchies, using a variety of high-speed interconnects. But moving all that data comes at a cost, creating cascading design constraints that extend from memory hierarchy decisions all the way to the power delivery network (PDN).

“As we move to backside and 3D stacking, heat becomes more localized and harder to dissipate,” said Julien Ryckaert, vice president of R&D at imec. “This physical compaction intensifies challenges like electromigration and localized thermal hotspots.”

To make power delivery tractable at these levels, multi-disciplinary design teams must think holistically about where and how voltage is regulated, how heat is extracted, how materials behave under high-current stress, and how much margin they have before electromigration and IR drop affect reliability. The complexity of these design decisions demands much tighter coupling between EDA tools, manufacturing processes, and advanced packaging.

“Today, high-performance compute and AI accelerators have crossed the kilowatt boundary,” said Jay Roy, chief architect at Synopsys. “Explosive growth in design complexity and shrinking cycles pose constant challenges for semiconductor SOC designs.”

This push to scale performance while minimizing power consumption is forcing big changes in power delivery models. It’s not just about reducing resistance anymore. It’s about modeling inductive behavior, thermal gradients, and coupling across materials with different coefficients of expansion. Early-stage predictions of voltage drops, current bottlenecks, and thermal hot spots are now essential, and they must be performed in the context of real layout and integration constraints.

From lateral to vertical power delivery
No amount of simulation solves the limitations inherent in traditional lateral power delivery. Routing high-current power traces laterally across the package and printed circuit board introduces losses and space constraints that no longer scale. This method was serviceable when chips consumed 100 or 200 watts, but it’s now a limiting factor for modern AI hardware.

“Current accelerator cards typically utilize a lateral power delivery architecture which route thousands of amps across centimeters of PCB traces, from the power module to the processor,” said Eelco Bergman, chief business officer at Saras Micro Devices. “This method results in significant power loss and excessive heat generation due to the high current and trace resistance. Additionally, the board real estate available to support the increasing total power, number of power rails, along with the routing of critical high-speed signals is limited.”

Fig. 1: Vertical power delivery network showing multi-domain capacitor modules embedded directly in the package substrate. Source: Saras Micro Devices

At these power levels, every milliohm of resistance translates into watts of heat that must be dissipated. Moreover, the spatial constraints imposed by lateral routing often create tradeoffs between power integrity and signal integrity. In high-bandwidth systems, where hundreds of high-speed SerDes lanes share board space with dense power planes, these tradeoffs become untenable.

To overcome those limitations, the semiconductor industry increasingly is exploring vertical power delivery. By embedding power rails or regulators directly under the die, and connecting them vertically with low-impedance paths, the distance from the source to the silicon shrinks dramatically. The result is reduced IR drop and noise, while freeing up top-side routing for critical signals.

“We are seeing customers actively exploring vertical power delivery architectures with embedded voltage regulation and integrated capacitive solutions that can localize power delivery,” added Bergman. “These approaches free up top-side PCB space, reduce parasitic losses, and increase overall power delivery performance.”

The use of integrated power delivery layers within the substrate and interposer, along with localized decoupling, enables AI chiplets and accelerators to receive cleaner, more stable power with less droop. Advanced substrates, including those with embedded passive devices, are now being co-designed with the silicon itself to optimize impedance profiles and thermal dissipation.

At the same time, these techniques pose new reliability challenges. Delivering high current through new materials and vertical structures requires rigorous modeling of current crowding, thermal cycling, and material fatigue. Embedded power elements must survive intense thermal flux while also remaining electrically isolated from sensitive signal layers. This, in turn, is driving innovation in dielectric materials, deposition techniques, and co-design methodologies.

Advanced packaging and thermal dissipation
High power density translates directly into thermal density, which can cause hot spots that degrade reliability and reduce performance. Without advanced heat extraction techniques, even the most efficient systems will require thermal throttling, which sharply reduces performance.

“Advanced packaging today employs multi-scale thermal management techniques to efficiently spread and remove heat,” said Gerard John, senior director of the Chiplets and Flip Chip Ball Grid Array (FCBGA) Business Unit at Amkor. “Indium alloy TIMs are particularly effective due to their high thermal conductivity of approximately 80 W/m-K. However, Indium TIMs require backside metallization of the die and the underside of the lid, typically with materials like Ti/Au or Ni/Au. A reflow process is necessary to create a bond between the die and lid, which helps reduce interfacial resistance.”

Minimizing the thermal resistance between the die and the heat spreader depends on the material and the application technique. Uniform TIM coverage and low-void processing are essential in achieving consistent heat removal across the die. Traditional solder-based TIMs are being replaced or supplemented by high-performance metal alloys, phase-change materials, and novel carbon-based interfaces.

“Ensuring minimal voids in TIM applications is crucial,” said John. “Voids can significantly impede thermal conductivity, leading to hot spots and reduced device reliability. Monitoring TIM voids is crucial in process optimization and device screening.”

These solutions often are tailored to specific workloads. AI training, for instance, generates longer sustained power bursts than inferencing and requires different thermal transient responses. Packaging engineers must collaborate with system architects to ensure that cooling solutions are matched to real-world operating profiles.

“TIM selection is often based on device power maps, which indicate areas of high heat generation,” John noted. “By matching TIM properties to these maps, optimal thermal management can be achieved, ensuring efficient heat dissipation across the device.”

In multi-chiplet systems, thermal challenges are magnified by the proximity of hot logic blocks. Advanced designs are turning to vapor chambers, microfluidic cooling, and double-sided heat extraction to manage this complexity. Each method introduces new manufacturing, reliability, and materials integration hurdles, but they are rapidly becoming essential tools for enabling AI performance at scale.

Molybdenum and material migration
As AI accelerators demand more power and tighter integration, traditional front-end materials are showing their age. The widespread use of tungsten and copper for local interconnects and contacts has been the industry standard for their conductivity and manufacturability, but it now imposes limitations in the densest parts of the chips.

This is where molybdenum is emerging as a critical replacement metal. With a shorter electron mean free path than copper, and better scalability in narrow geometries than tungsten, molybdenum offers tangible improvements in both resistivity and manufacturability at advanced nodes.

“Transitioning from traditional tungsten metallization to molybdenum provides substantial performance improvements, including up to 50% lower contact resistance,” said Kaihan Ashtiani, corporate vice president and general manager at Lam Research. “Molybdenum’s shorter electron mean free path makes it superior for smaller dimensions, significantly reducing resistance issues in tightly packed interconnect structures.”

What this means in practice is that molybdenum becomes especially advantageous in local interconnects, where line widths and spacings are now below 20nm. At those dimensions, conventional metals like tungsten suffer from increased electron scattering, which leads to higher effective resistivity and thermal load. Molybdenum, by contrast, maintains favorable conduction behavior in confined geometries.

For AI devices, this property is critical. As more functionality is packed into fewer square millimeters, and with vertical stacking becoming more common, heat and resistance are increasingly localized. Material innovations like molybdenum help mitigate these effects, both by improving electrical performance and simplifying integration into atomic layer deposition (ALD) and chemical vapor deposition (CVD) processes that already are common in leading-edge fabs.

“When interconnect dimensions shrink below the mean free path of a metal like copper, resistance increases due to more frequent electron scattering,” said Ashtiani. “In those cases, a metal like molybdenum, with a shorter mean free path, actually becomes more favorable, because it maintains lower resistance at smaller scales.”

The shift to molybdenum also is aligned with broader industry efforts to reduce electromigration risks. At high current densities common in AI workloads, metal migration can create voids and open circuits over time, which is a growing concern for reliability. Molybdenum’s high melting point and grain stability help counteract this, making it a strong candidate for long-lifetime AI compute applications.

While not yet universal, the adoption of molybdenum is accelerating, particularly in applications with extreme power densities, such as GPU matrix engines and SRAM arrays. It also is gaining traction in devices that incorporate backside power delivery, where the complexity of metallization layers demands highly conformal and low-resistivity materials.

Backside power delivery
Perhaps the most transformative shift in chip architecture today is the move to backside power delivery networks (BSPDNs). Instead of routing both power and signals through the top metal layers where they compete for real estate, BSPDNs decouple these functions by introducing power connections on the underside of the wafer.

The original concept, first publicized by Intel as “power vias,” has since evolved into a broader class of technologies being adopted across the industry. In essence, the backside of the wafer is etched to expose contacts, which are then used to deliver power directly to the transistors, bypassing the signal routing stack and dramatically improving efficiency.

“Backside power delivery began with power vias etched into silicon to provide direct power access from the back side, which helps reduce impedance,” said imec’s Ryckaert. “Processing wafers from both sides opens new opportunities for device scaling and routing density, although it also introduces thermal challenges due to the removal of silicon as a heat spreader.”

This structural reorganization offers several key advantages for AI chips. First, by separating power and signal routing, engineers gain more flexibility in floor-planning and timing optimization. Signal layers can be expanded or fine-tuned without worrying about power distribution constraints. Second, it enables thinner and more uniform power grids, which reduces IR drop and makes voltage regulation more predictable.

“Power delivery used to be one of many considerations,” Ryckaert added. “Now it shapes the entire floorplan. Backside PDNs help decongest routing and enable higher transistor density, but they also increase power density, which makes thermal management more critical than ever.”

In addition, backside processing introduces new options for cooling. Because the silicon substrate no longer acts as a barrier to heat dissipation, designers can implement double-sided cooling strategies, where thermal interfaces are applied to both sides of the die.

However, backside power delivery is not without its challenges. It requires entirely new process flows and material advancements, including wafer thinning, through-silicon via (TSV) alignment, hybrid bonding, and handling of extremely fragile dies. The mechanical reliability of these structures is still being studied, and yield optimization remains a barrier to high-volume adoption.

Design co-optimization and system-level impacts
Despite the technological promise of backside power, molybdenum interconnects, and vertical PDNs, none of these advances happen in isolation. The next generation of AI chips will require a more tightly integrated approach across the design stack, using what is generally known as system technology co-optimization (STCO).

In this model, silicon architects, packaging engineers, and system designers collaborate from the earliest design stages. Power delivery networks, thermal profiles, mechanical stresses, and floorplans must be modeled as interdependent systems, not sequential steps in a flow.

“Power-aware co-design is increasingly essential,” said Synopsys’ Maben. “It helps balance thermal performance with timing closure, allowing customers to achieve better efficiency and reliability in the final product.”

At the system level, these optimizations have broad consequences. Thermal throttling, for instance, is one of the biggest threats to AI chip performance. Without effective prediction and mitigation of localized heating, otherwise well-designed systems can underperform in the field.

“A marginal improvement in power delivery efficiency upstream can prevent thermal degradation downstream,” said Synopsys’ Roy. “The goal is to give engineers early visibility into how these systems interact so that reliability is built in, not bolted on.”

This has implications far beyond the die. System integrators must consider PDN impedance across the full stack — dies, interposers, substrates, and PCBs. Signal integrity, board-level decoupling, and enclosure-level airflow all influence whether a power-efficient chip will perform as intended in a real-world.

These constraints have elevated the importance of co-simulation and cross-domain feedback loops. Voltage integrity and electromagnetic interference (EMI) now intersect directly with thermal simulation, materials modeling, and power-aware verification. In response, some chipmakers are bringing packaging and system engineering teams in-house, or embedding them within chip design teams to speed iteration and ensure consistency.

Beyond technical coordination, economic incentives drive co-optimization, as well. Over-provisioning a power delivery system by adding excess capacitance, wider power planes, or over-engineered VRMs consumes board area and resources that otherwise could go to compute.

“Reducing IR drop and improving power delivery efficiency translates directly into less heat and lower cooling costs,” said Saras’ Bergman. “That’s a direct cost advantage in hyperscale data centers.”

Conclusion
As AI demand grows, the pressure to optimize every watt, and every dollar spent delivering it, will only intensify. This means power delivery is no longer a back-end consideration. It has become a front-line constraint shaping how AI chips are designed and manufactured. As AI chips push into the kilowatt regime, the industry must rethink everything from materials to floor plans to wafer bonding to thermal dissipation. Innovations like backside power delivery networks, molybdenum interconnects, and vertically integrated substrates are just the beginning.

The path forward in power delivery for AI chip requires deep collaboration across disciplines. The silos that have been built around silicon, packaging, and system design are dissolving as engineers confront the multi-physics nature of next-generation power delivery. And while the cost and complexity of these solutions are high, the payoff — measured in performance, efficiency, and scalability — will be enormous.

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