Practical Methods To Overcome The Challenges Of 3D Logic Design

What should you do If you don’t have enough room on your floor to store all your old boxes? Luckily, we live in a 3D world, and you can start stacking them on top of each other.

The Challenge: How can we shrink logic devices?
Logic designers are currently facing even bigger challenges than you might be having in tidying up your storage area. Not only are logic cells highly packed together already, but in addition their sizes are constantly required to shrink. Logic designers can increase the density of devices by re-engineering logic to generate new white space areas on their logic cells. This white space can be subsequently removed, in effect increasing the density of the device. When component (transistor) level scaling cannot shrink sizes any further, designers need to find other scaling boosters. Luckily, logic designers have another alternative to increase the density of their designs. We live in a 3D world, and we can think about designing in three dimensions to increase device performance over that of current 2D designs.

The Promise of 3D Logic Design
Using the Z-axis in cell design can indeed overcome current X-Y density constraints. The strongest approach, in terms of real estate gain, is to bring transistor-level components on top of each other, rather than using the classical side by side design methodology.  This can be accomplished by placing an n-Field Effect Transistor (FET) on top of an n-FET, or p- on p-, or even a Complementary FET (CFET) with n- on p- or p- on n- . The FET transistors being used can be any flavor of FET (planar, fin, nanosheet, nanowire) when designing in the Z-axis.

3D logic design offers many new opportunities to improve logic scaling and density, but not without its challenges. To succeed, design circuitry must be completely re-engineered and advanced process development is required. For example, two levels of transistors can be processed separately on two different wafers and these can subsequently bonded face-to-face, using TSVs (through-silicon vias) to connect the two levels of the device. A sequential technology (suggested by CEA-LETI’s CoolCube) is an alternative approach, where the top-level transistor is processed after wafer bonding. This year at the VLSI conference, imec presented a third very innovative integration option, which is monolithic and requires no wafer bonding step.

The Practical Problems of 3D Logic Design
CD and variation issues in logic design and manufacturing are limited to the X-Y plane in conventional 2D semiconductor design.   Imposing constraints on lithography and etch overlay/bias control are important, since these can be large sources of variability.  In 3D logic design, CD and variation control is additionally required on the Z axis. Control and uniformity of deposition thickness and etch depth will be critical when moving logic to 3D structures. Process integrators will ideally be aware of and address these new process issues, prior to spending time and money during wafer processing of 3D logic.

Coventor’s SEMulator3D software offers two key capabilities to help in this task. 3D Visualization and Virtual DOE (Design of Experiments) can help process integrators avoid unnecessary cycles of wafer-based testing during the development of new, 3D logic.

3D Visualization
Thinking in 3D can be challenging, but sharing 3D ideas, concepts and drawings with colleagues on a white board is even more difficult. This is a real challenge for many process integrators, who need the ability to rotate, zoom in/out, slice and cross section their device structures prior to and during fabrication. One of the most commonly used features of SEMulator3D is 3D Visualization. Using a combination of the process flow file and a layout file, a device can be virtually fabricated in 3D using advanced geometrical models. Many methods of visualization and metrology are then possible within the 3D virtual architecture.

SEMulator3D visualization also enables designers to highlight 3D process/design interaction risks that cannot necessarily be detected in a 2D drawing. This is illustrated in Fig 1 (a-c), with an example of a 3D device built virtually in SEMulator3D. The CFET architecture shown has two levels of transistors, two M0 metal levels (one for each transistor level), and a buried power rail as an additional scaling booster. Fig 1.a is a 2D cross-section of the structure showing a continuous nitride layer which isolates the two M0 layers (as expected within the design). Fig 1.b (animation) illustrates typical rotation and cross section motions that SEMulator3D offers within a 3D structure. This allows a user (with the help of SEMulator3D’s Structure Search feature) to detect a short (as shown in Fig 1.c) between the two M0 levels at a specific location (close to the Via connecting the top M0 level to the buried rail). That specific short could not have been detected without the use of 3D visualization.

Fig 1.a. CFET Cross section showing a continuous nitride layer isolating the two M0 levels (top and bottom).

Fig 1.b. (animated gif) Structure rotation and cross section change done by SEMulator3D to look for short within the 3D structure.

Fig 1.c. Short between the two M0 levels identified by going through the 3D structure (Fig 1.b) – this failure was not seen on the 2D cross section from Fig 1.a.

Virtual DOE (Design of Experiments)
Learning by experimentation (wafer fabrication) is a standard method to provide intelligent, data-driven feedback in semiconductor design. However, each such experimental wafer run has an inherent (and large) associated time and cost. Due to this high cost, process integrators often need to make risky technology decisions based upon a limited amount of data from experimental DOEs (Design of Experiments). Most of the time, only a handful of process parameters can be screened on a few wafers due to the time and cost of wafer-based testing.

Decision making can be easier, faster and safer if a larger amount of statistical data can be produced using process modeling and virtual DOEs. SEMulator3D can be used to select variables (input process parameters) and launch virtual DOEs to rapidly produce statistical quantities of virtual experimental data.   Users can explore a range of process parameter values in each simulation or DOE run, to see the effect of process changes on device performance. Virtual metrology can be used to measure any parameter of interest (structural or electrical) for each of those DOE runs. SEMulator3D has an Analytics Module that can be used to identify and optimize process windows.

Identifying Significant Design and Process Variables

The Analytics Module in SEMulator3D can:

Launch DOEs (either Definitive Screen Design, Full Factorial, Monte Carlo with uniform distribution or Monte Carlo with normal distribution) automatically after selection of the variables and their ranges.

Perform complete data analytics using regression models and sensitivity analysis, in order to understand the impact of each variable on metrology results and device performance.

As an example, we will review a process sensitivity assessment that was performed on a monolithic CFET device. Eleven variables (process parameters such as dielectric/EPI/metal/resist thicknesses and etch depths) were selected and screened using 200 simulation runs in SEMulator3D. The variables were analyzed over their current process range (provided by the customer) and a uniform distribution of events was assumed within a Monte Carlo virtual DOE. Virtual metrology was also configured to measure two critical parameters in the flow: the elevations of two layers (identified as Layer 1 and 2). Once the 200 simulations were complete, the Analytics Module was used to execute a regression model and classify the impact of each variable (and their products) on the two elevation values. The significant variables from this analysis have been highlighted in Fig 2.

Fig 2: Illustration of the Analytics platform in SEMulator3D, displaying a regression model and ranking of variables based upon their impact on specified virtual metrology targets.

Moving the sensitivity analysis one step further, Fig 3 shows the independent impact of each of the 11 variables on the elevation of the two measured layers. Upper Level Control (ULC) and Lower Level Control (LLC) on those two elevations are defined by design rules and are identified using the horizontal red dotted lines. From those limits, we can easily re-define new targets and ranges required for each of the 11 variables (vertical black dotted lines).

As shown in Fig 3, certain process parameters (Metal_Recess_3, Resist_Thickness_1, Resist_Recess_1) will require specification tightening with respect to current process limits. SEMulator3D’s virtual DOEs can help identify new requirements (or limits) of process control and uniformity prior to fab-based testing. One of the most significant benefits in this technique is that virtual data can be used to identify where the entire supply chain should be engaged on new tool and materials specification requirements during the design phase, instead of having to wait until years of experimental wafer fabrication data has been completed.

Fig 3: Independent impact of each variable on the two-layer elevations measured by virtual metrology. Horizontal red doted lines are limits defined by design rules. Vertical black doted lines are new specifications determined for each of the variables.

Summary
In summary, SEMulator3D offers two key features (3D Visualization and Virtual DOE) which can highlight 3D process/design interaction risks, define required process control and uniformity, and recommend process/design corrections to ensure the success of a new semiconductor design. These features of SEMulator3D are particularly useful during the development of advanced 3D logic technologies such as those discussed in this article.