Quiet, Steady And Sometimes Unexpected Advances For SOI

By Ed Sperling
After years of talking about equivalent pricing, technical advantages and consistent processes, silicon on insulator finally appears to be making significant inroads—but not necessarily in ways, places, or even at process nodes where it initially was predicted to gain ground.

What’s driving at least some of this change is the semiconductor industry’s progression toward stacked die, where commercially available die will be produced in whatever process and on whatever substrate makes the most sense for the manufacturer. What wins the socket—or at least the layer or space in the package—will be price, energy efficiency and performance, although not necessarily in that order. In most cases, however, that means new materials rather than bulk CMOS.

Consider the Hybrid Memory Cube, for example. While the majority of attention being paid to the 3D memory architecture is at the DRAM level, the logic base layer—in this case made by IBM—uses an SOI substrate. And while the initial application is for enterprise applications, where high performance and low power are critical and pricing is less of an issue, there already are discussions underway between Micron and a number of other vendors beyond just the data center.

Scott Graham, general manager of hybrid memory at Micron, said the next generation of the HMC will be in production by the end of next year, with volume applications using 3D-ICs with TSVs in 2015 or 2016. But he said the existing HMC architecture also can be attached to FPGAs, either in a vertical stack or in a 2.5D configuration. The result is that SOI becomes an integral part of 2.5D and 3D stacks, even if some of the other pieces use different materials.

“You can attach the cubes to each other or to FPGAs,” said Graham. “We’re looking at a variety of flexible architectures and protocols.”

Having an additional layer of insulation is a bonus in that architectural arrangement, as well, to buffer against a variety of physical effects ranging from noise to heat—as long as the heat doesn’t get trapped inside a device. So far, the existing architectures allow for heat to escape through exposed sides of the device. In stacked die, getting the heat out requires a variety of architectural approaches ranging from using TSVs as chimneys to using more exotic and expensive approaches such as liquid cooling within a die with microfluidics.

From planar to stacked die
SOI—as well as other substrate materials—are showing up in planar devices, as well. Companies wrestling with a compendium of physical effects at the leading edge of Moore’s Law say that for most applications new materials will be necessary going forward.

Intel remains the poster child of bulk CMOS. It steadfastly has resisted changing from bulk CMOS. But Intel’s architecture also is much more regular and redundant than most others being developed in the IC world. Systems on chip have many more irregular subsystems, which may or may not be on at any given time, and which frequently generate heat, electromagnetic interference and noise in an inconsistent manner that in some cases is determined by user preferences. That causes some parts of the chip to heat up while others remain cool, and with gate oxides now measured in Angstroms additional insulation is considered a very good thing.

Solving all of those problems with guardbanding, the necessary architectural changes, and being able to obtain sufficient yield are difficult, time-consuming and expensive.

“The cost issue is a tough one to deal with from a technology point of view,” said Chenming Hu, professor at UC Berkeley who is considered the father of the finFET. “I believe the world be willing to pay more if none of the semiconductor companies can continue to slash prices. And from a performance/power consumption perspective, I feel quite confident this industry will continue to grow. In the immediate future, finFETS and UTB/ET/FD-SOI are very exciting technologies.”

STMicroelectronics already has begun productizing FD-SOI at 28nm. “We are in the low-power SoC space, and particularly with our subsidiary ST-Ericsson in the mobile computing space, we were looking for a solution that could provide differentiation in terms of efficiency,” said Philippe Magarshack, ST’s corporate vice president of design enablement and services. “We identified planar SOI as the next step going forward. We also identified with our customers what would be the sweet spot for our customers. We had working test chips earlier this year that confirmed our decision to move forward. Our decision was to put a product on the market as soon as possible for the next-generation applications processor.”

He said that one significant advantage of using SOI is the ability to polarize the back edge. “There is more design involved, but we get a 20% boost in efficiency right off the bat. With back-gate biasing you get 30% to 35% boost at high Vdd, and 80% boost at low Vdd. We have use cases in cell phones where the battery life is extended by 30% to 40%. This is a significant benefit.”

IBM holds a similar view, particularly at 20nm.

“We see this really addressing two areas in the SoC space,” said Gary Patton, vice president of IBM’s Semiconductor Research and Development Center “One is that the cost of migrating designs into the next technology node is becoming extremely expensive. The ability to take 28nm technology and do a fairly straightforward migration to FD-SOI and get an immediate performance boost is extremely attractive. But the value proposition of 20nm planar technology has been disappointing for many customers both in terms of cost, because of double patterning, as well performance. Being able to apply FD-SOI to 20nm significantly enhances that value proposition.”

The future
The combination of finFETS plus different substrates provides a couple knobs to turn to reduce leakage and minimize heat. Add that to stacked die, where bigger pipes require less power to drive signals over shorter distances, and the picture becomes even more appealing.

As Micron’s Graham noted, SOI is just a first step in what will likely be a much more rational use of materials to solve very specific problems in stacked die. SOI is an important material, but it is just one of many now under consideration. Nevertheless, it does solve problems for at least a couple more process nodes and in stacked configurations, and at this point most leading edge companies say it is the least-expensive proven solution.