Research Bits: May 10

Growing 2D TMDs on chips

Researchers from Massachusetts Institute of Technology (MIT), Oak Ridge National Laboratory, and Ericsson Research found a way to “grow” layers of 2D transition metal dichalcogenide (TMD) materials directly on top of a fully fabricated silicon chip, a technique they say could enable denser integrations.

The researchers focused on molybdenum disulfide, which is flexible and transparent with good electronic and photonic properties. Typically, the process requires temperatures over 550 degrees Celsius, far higher than the 400 degrees above which silicon transistors and circuits could break down.

Key to the technique is a new furnace for the metal-organic chemical vapor deposition process. The oven consists of two chambers, a low-temperature region in the front, where the silicon wafer is placed, and a high-temperature region in the back. Vaporized molybdenum and sulfur precursors are pumped into the furnace. The molybdenum stays in the low-temperature region, where the temperature is kept below 400 degrees Celsius — hot enough to decompose the molybdenum precursor but not so hot that it damages the silicon chip.

Graduate student Jiadi Zhu holding an 8-inch CMOS wafer with molybdenum disulfide thin film. On the right is the furnace the researchers developed, which enabled them to “grow” a layer of molybdenum disulfide onto the wafer using a low-temperature process that did not damage the wafer. (Image: Courtesy of the researchers / MIT)

The sulfur precursor flows through into the high-temperature region, where it decomposes. Then it flows back into the low-temperature region, where the chemical reaction to grow molybdenum disulfide on the surface of the wafer occurs.

“You can think about decomposition like making black pepper — you have a whole peppercorn and you grind it into a powder form. So, we smash and grind the pepper in the high-temperature region, then the powder flows back into the low-temperature region,” said Jiadi Zhu, an electrical engineering and computer science graduate student at MIT.

To prevent sulfurization of the aluminum or copper top layer, they first deposited a very thin layer of passivation material on top of the chip. Then later they could open the passivation layer to make connections.

They also placed the silicon wafer into the low-temperature region of the furnace vertically, rather than horizontally. By placing it vertically, neither end is too close to the high-temperature region, so no part of the wafer is damaged by the heat. Plus, the molybdenum and sulfur gas molecules swirl around as they bump into the vertical chip, rather than flowing over a horizontal surface. This circulation effect improves the growth of molybdenum disulfide and leads to better material uniformity.

The low-temperature method not only grows a smooth, highly uniform layer across an entire 8-inch wafer, it takes less than an hour – much faster than previous approaches.

“By shortening the growth time, the process is much more efficient and could be more easily integrated into industrial fabrications. Plus, this is a silicon-compatible low-temperature process, which can be useful to push 2D materials further into the semiconductor industry,” Zhu says.

In the future, the researchers want to fine-tune their technique and use it to grow many stacked layers of 2D transistors. In addition, they want to explore the use of the low-temperature growth process for flexible surfaces, like polymers, textiles, or papers to enable the integration of semiconductors onto everyday objects like clothing or notebooks.

Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform: https://doi.org/10.1038/s41565-023-01375-6

Sputtering spintronics

Researchers from the University of Minnesota Twin Cities and the National Institute of Standards and Technology (NIST) developed a new process for making spintronic devices. Spintronics utilize the spin of electrons rather than the electrical charge to store data.

“We believe we’ve found a material and a device that will allow the semiconducting industry to move forward with more opportunities in spintronics that weren’t there before for memory and computing applications,” said Jian-Ping Wang, professor in the University of Minnesota Department of Electrical and Computer Engineering.

The researchers said cobalt iron boron, the standard spintronic materials, has reached a limit in its scalability, with devices unable to be smaller than 20 nanometers without losing their ability to store data.

Instead, they turned to iron palladium, which can be scaled down to sizes as small as five nanometers. It also requires less energy and has the potential for more data storage.

They were able to grow iron palladium on a silicon wafer using an 8-inch wafer-capable multi-chamber ultrahigh vacuum sputtering system. “This work is showing for the first time in the world that you can grow this material, which can be scaled down to smaller than five nanometers, on top of a semiconductor industry-compatible substrate, so-called CMOS+X strategies,” said Deyuan Lyu, a Ph.D. student in the University of Minnesota Department of Electrical and Computer Engineering.

Sputtered L10-FePd and its Synthetic Antiferromagnet on Si/SiO2 Wafers for Scalable Spintronics: https://doi.org/10.1002/adfm.202214201

Detecting hardware Trojans

Researchers from Ruhr University Bochum, Max Planck Institute for Security and Privacy (MPI-SP), and Université catholique de Louvain explored using scanning electron microscope (SEM) images and image processing algorithms to detect the presence of hardware Trojans. Using their method, they were able to detect deviations in 37 out of 40 cases.

The team analyzed chips manufactured at 28nm, 40nm, 65nm, and 90nm process nodes. By using chips previously produced at Ruhr University Bochum, they had access to both the manufactured chips and the design files.

The original designer of the chips modified the GDSII layout files to create minimal deviations from the fabricated chip, either replacing filler cells by functional standard cells or substituting existing cells with cells of a different functionality.

The other researchers then imaged the chips using a scanning electron microscope. “Comparing the chip images and the construction plans turned out to be quite a challenge, because we first had to precisely superimpose the data,” said Endres Puschner, a security expert at MPI-SP. In addition, every little impurity on the chip could block the view of certain sections of the image. “On the smallest chip, which is 28 nanometers in size, a single speck of dust or a hair can obscure a whole row of standard cells.”

They then used image processing methods to match standard cell for standard cell and look for deviations between GDSII and SEM. “The results give cause for cautious optimism,” said Puschner. For the 90, 65, and 40 nm chips, the team successfully identified all modifications. The number of false-positive results, where standard cells were flagged as having been modified when they weren’t, totaled 500. “With more than 1.5 million standard cells examined, this is a very good rate,” added Puschner. In the 28nm chip, the researchers failed to detect three changes.

Better SEM equipment and use of a clean room could improve the results, noted Steffen Becker of Ruhr University Bochum. “We also hope that other groups will use our data for follow-up studies. Machine learning could probably improve the detection algorithm to such an extent that it would also detect the changes on the smallest chips that we missed.”

The researchers released all images of the chips, the design data, and the analysis algorithms online for free so that other research groups can use the data to conduct further studies.

Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations: https://eprint.iacr.org/2022/1720