Benchmarking 3D-IC cooling; rad-hard flip-flops; high-speed data error correction.
Researchers from Massachusetts Institute of Technology (MIT) and HRL Laboratories developed a specialized chip to test and validate cooling solutions for packaged chip stacks.
The chip dissipates extremely high power, generating heat through the silicon layer and in localized hot spots to mimic high-performance logic chips. It then uses diodes to measure temperature changes as cooling is applied to the packaged stack.
“If you have just a single chip, you can cool it from above or below. But if you start stacking several chips on top of each other, the heat has nowhere to escape. No cooling methods exist today that allow industry to stack multiples of these really high-performance chips,” said Chenson Chen, part of MIT Lincoln Laboratory’s Advanced Materials and Microsystems Group.
The team anticipates using the chip to benchmark methods of cooling 3D heterogenous integrated systems that combine silicon with non-silicon RF components. [1]
Researchers from Carnegie Mellon University and Sandia National Labs fabricated more compact radiation-hardened chips that achieve equivalent or better radiation tolerance as conventional radiation-tolerant designs.
The effort focused on improving the error tolerance of flip-flops (FF) in eFPGAs. “As FFs are one of the most common elements on a chip, reducing the area of the FF has a significant reduction of the overall chip area,” said Ken Mai, principal systems scientist in the electrical and computer engineering department at Carnegie Mellon, in a press release. “Lower area leads to lower manufacturing costs, higher performance, and better energy efficiency, which is particularly important for space applications.”
Key to the innovation is not the transistors themselves, but their arrangement. “Traditional robust FF designs use triple modular redundancy, majority vote of three copies of the same circuit block, to ensure error free operation. This updated design re-uses some of the components of a single basic FF to achieve the same level of radiation tolerance without the high area overhead of using three copies of the FF,” said Carnegie Mellon’s Krista Burns, in a press release.
The team is designing full SoC prototypes and plans to test and deploy on a cubesat in 2026. [2]
Researchers from Oregon State University designed and fabricated a chip that makes running large language models (LLMs) more efficient by reducing the energy used for signal processing.
“Large language models need to send and receive tremendous amounts of data over wireline, copper-based communication links in data centers, and that requires significant energy,” said Ramin Javadi, a doctoral student at OSU, in a press release. “One solution is to develop more efficient wireline communication chips.”
The approach targets the corruption that happens at the receiver end when data is sent at high speeds. Most conventional wireline communication systems use an equalizer to clean up the data, which is comparatively power hungry. “We are using those AI principles on-chip to recover the data in a smarter and more efficient way by training the on-chip classifier to recognize and correct the errors,” Javadi said. [3]
[1] Ryan Keech, Chenson Chen, Chad Stark, et al. “Custom Si Chip Fabrication to Benchmark Local Temperatures within 3D Heterogeneously Integrated Stacks.” Government Microcircuit Applications and Critical Technology Conference (GOMACTech) 2025.
[2] Prashanth Mohan, Siddharth Das, Oguz Aatli, et al. “A Soft Error Tolerant Flip Flop for eFPGA Configuration Hardening in 22nm FinFET Process.” Design, Automation, and Test in Europe, March 31, 2025, Lyon France.
[3] Ramin Javadi, Tejasvi Anand. “A 0.055pJ/bit/dB 42Gb/s PAM-4 Wireline Transceiver with Consecutive Symbol to Center (CSC) Encoding and Classification for 26dB Loss in 16nm FinFET.” 2025 IEEE Custom Integrated Circuits Conference.
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