Searching For 3D Metrology

In the previous decade, chipmakers made a bold but necessary decision to select the finFET as the next transistor architecture for the IC industry.

Over time, though, chipmakers discovered that the finFET would present some challenges in the fab. Deposition, etch and lithography were the obvious hurdles, but chipmakers also saw a big gap in metrology.

In fact, the metrology tools were capable of measuring structures in two dimensions, and in three dimensions to some degree, but that was not nearly good enough for the complexity of finFETs. Unlike traditional planar transistors, finFETs have an assortment of three-dimensional structures that are difficult to measure.

So to fill the gap, the industry over the years has been working on a new class of so-called 3D metrology tools, which supposedly can measure both two- and three-dimensional structures in a cost-effective manner.

Today, the big question is clear: Is the industry there yet in 3D metrology? The answer is less clear. Current metrology tools can provide more three-dimensional measurements than before. But as before, there is no single system that can do everything.

All told, chipmakers have found solutions to address the challenges with finFETs, but it requires a growing list of in-line metrology tools just to keep up with device complexity. This includes nearly a half-dozen systems based on X-ray techniques, which are sometimes a slow and cumbersome process.

“The number of measurement steps has been increasing exponentially,” said Alok Vaid, manager of optical metrology at GlobalFoundries. “We are piling on more in-line metrology techniques because of the need. The need is not just to measure smaller dimensions, but it’s also about the complex integration schemes.”

There are other challenges as well. “We’re seeing an explosion of process layers,” said Brian Trafas, chief marketing officer at KLA-Tencor. “We are also seeing many types of complex film stacks.”

Going forward, the metrology community will require more breakthroughs to address current and future devices. In fact, there are still many gaps in the flow, such as in-die metrology and X-ray tool productivity.

Planar to finFETs
For decades, the industry has used planar transistors in IC designs. But at 20nm, planar is hitting the wall due to short-channel effects. So, the industry is moving towards finFETs. “The finFET provides much lower power,” said Kelvin Low, senior director of foundry marketing for Samsung Semiconductor. “The channel, where the current flows, is 3D. We had to make it 3D so that the amount of current flowing in the area increases.”

Still, finFETs present some challenges in IC manufacturing. “We have to resort to immersion multi-patterning technology,” Low said. “There is no other way around it.”

The challenges will escalate at 10nm and beyond. “It’s not just lithography. There are many other questions going forward, such as alignment, edge placement error and metrology,” said Girish Dixit, vice president of process applications for LAM Research. “When you start measuring such small features, then you talk about consistency and control for that pattern. Control is becoming a bigger component of the overall engineering work the industry will need to do.”

In fact, metrology, the science of measuring and characterizing tiny structures and materials, is becoming more complex and expensive at each node. In total, the process control sampling rates in the fab have increased by 80% from 130nm to today’s leading-edge processes, according to Canaccord Genuity.

At 45nm, chipmakers used the traditional metrology tools for planar devices. These tools included atomic force microscopy (AFM), the critical-dimension scanning electron microscope (CD-SEM), film-thickness systems and optical CD (OCD).

In finFETs, however, a given metrology tool must make 12 or more different measurements, such as the gate height, fin height and sidewall angle. Each of those parts also requires one or more separate measurements.

For finFETs, metrologists use the traditional tools. In addition, they must also use model-based infrared reflectometry (MBIR), transmission electron microscopy (TEM), and several X-ray tool technologies. And if that isn’t enough, metrologists are attempting to bring a new technology called hybrid metrology into the flow.

The technologies
So how are metrologists tackling the complexities of finFETs today? One traditional tool, the CD-SEM, uses a focused beam of electrons to generate signals at the surface of a structure. The CD-SEM is a key metrology tool for planar transistors, but at one time, these systems could only do limited work for finFETs. The tool could measure the fin widths, but it could not image the fin height and the sidewall angle.

As a result, the CD-SEM was on the outside looking in for finFETs. And, in fact, OCD grabbed the lion’s share of the measurements in the finFET metrology flow, at least in the early stages of the ramp. One common type of OCD, dubbed scatterometry, measures the changes in the intensity of light.

The CD-SEM suppliers, however, have recently fought back by adding tilt-beam capabilities to the tool. “There are two major breakthroughs on the CD-SEM side,” said GlobalFoundries’ Vaid. “The breakthrough is to get 3D information out of 2D imaging. One way to do that is to do a tilt. Rather than looking top down, you look slightly at an angle. Now, it can measure height and the sidewall angle. It still cannot measure other parameters, which OCD does. But it does fill a critical gap.”

Applied Materials, for one, has added tilt-beam technology to its CD-SEM tool, enabling it to get a piece of the action in the finFET metrology flow. “Now, the trend is changing,” said Ofer Adan, global product manager at Applied Materials. “OCD is not going to vanish, but what we are seeing is that high-k/metal-gate brought metal into the game. Metal and OCD do not go very well together. The metal is confusing the optics. The dimensions of the gate over the fin are becoming too complex for OCD.”

All told, chipmakers are using OCD for some applications and the CD-SEM for others. “OCD is doing the fins well. But in regard to gate over the fin, (OCD) is not doing very well. It is taking too long in development. It is also losing the correlations between in-die and scribe,” Adan said. “CD-SEM is doing gate over the fin very well. That’s going to be the bread-and-butter application for the CD-SEM.”

Chipmakers are also using the CD-SEM for another piece of the puzzle—the interconnect. Using backscattering techniques, the CD-SEM is being used for measurements in the dual damascene structure, he added.

OCD is not standing still, however. The knock on OCD is that chipmakers must develop complex and time-consuming models. “Most of them, especially the model-based ones like OCD, thickness and MBIR, need reference data to calibrate. If you don’t reference the data, you can’t use these techniques,” GlobalFoundries’ Vaid said.

One way to obtain reference data is to cut the wafer and do a cross section of the device using a TEM. “What we are finding is that the TEM process is becoming more expensive and is becoming a gating factor,” Vaid said.

In response, GlobalFoundries and its partners have developed a technique that can predict the reference data from a TEM. “If you can predict that, you save a lot time and costs,” he said. “We will use more advanced analytic modeling solutions to give us more information and solve our time to solution problems.”

OCD is addressing other challenges. “There is always going to be room for CD-SEM, but you really need optical CD for some of these complicated 3D structures,” KLA-Tencor’s Trafas said. “FinFETs, as an example, have multi-layer stacks, but they are very thin. On a finFET, if I have a slight deviation on the film layer, it could dramatically change the performance of the device.”

KLA-Tencor, a supplier of OCD and other tool types, has recently rolled out the SpectraFilm LD10 system that can address the film-stack challenge. The tool can support wavelengths from deep ultraviolet to infrared (IR). “We’ve taken IP from our inspection platform. It has a very bright source and it’s broadband. It goes from 190nm into the IR wavelengths. In finFETs, I can use deep UV to measure those thin oxide layers,” Trafas said.

Still, there are some remaining gaps with OCD. Generally, the tools don’t measure the actual product. Instead, they measure a representative, or scribe, structure. The measurements between the scribe structures and the actual devices are supposed to match. “For advanced nodes, especially 3D devices, the correlations start to break,” GlobalFoundries’ Vaid said. “We need in-die measurement techniques. We have a gap there.”

To a limited degree, AFM and CD-SEM can support in-die metrology. OCD is playing catch-up. KLA-Tencor, for one, is addressing the in-die metrology issues. The company recently rolled out a new overlay metrology tool, which makes use of small targets, including in-die targets.

Another gap is the productivity of the vast array of the X-ray metrology tools used in the finFET flow. In the flow, chipmakers use the following technologies—high-resolution X-ray diffraction (HRXRD); low-energy electron induced X-ray
emission spectrometry (LEXES); X-ray fluorescence (XRF); X-ray photoelectron spectroscopy (XPS); and X-ray reflectivity (XRR).

“All of these X-ray tools are lab tools. Now, we are putting them in-line to measure these new processes,” Vaid said. “In some cases, they are production-worthy. In other cases, no. Some of them are learning and getting better.”

In one step to address the issues, OCD tool vendor Nova Measuring Instruments recently acquired ReVera, a supplier of XPS-based tools. One of Nova’s goals is to boost the productivity of XPS. Used to measure the critical and compositional properties of a film or surface, XPS illuminates a surface with low energy X-rays.

Ultimately, though, there is no one tool that can handle all metrology needs for finFETs. So for some time, chipmakers have been talking about a technology called hybrid metrology. In this approach, chipmakers use a mix-and-match of several different tool technologies and then combine the data from each. In one example, a finFET structure is measured by both the CD-SEM and an AFM. Then, the results are fed into an OCD tool to validate the model.

Hybrid metrology, though, is still in the early stages of development. The challenge is to put rival tools in the same flow and tell competitors to collaborate.

Nonetheless, chipmakers will require more collaboration in metrology in one form or another. Otherwise, IC makers will continue to wrestle with finFET production. “Collaboration is very important. We cannot generate everything ourselves,” Vaid said.