Centered on the multibit devices, a shared-write-channel (SWC) memory design provides double the device density of current SOT magnetic random-access memory (MRAM).
ABSTRACT
“Spin-orbit-torque (SOT) devices are promising candidates for the future magnetic memory landscape, as they promise high endurance, low read disturbance, and low read error, in comparison with spin-transfer torque devices. However, SOT memories are area intensive due to the requirement for two access transistors per bit. Here, we report a multibit SOT cell that has a single write channel shared among multiple bits, which enables an area-efficient memory design by reducing the number of access transistors. All combinations of digital information can be written in the multibit devices with a single current pulse. This functionality is facilitated by the electric field modulation of SOT polarity by tuning the heavy metal-ferromagnet interfacial oxidation state. Centered on the multibit devices, a shared-write-channel (SWC) memory design provides double the device density of current SOT magnetic random-access memory (MRAM). This improvement makes SOT MRAM appealing for its adoption over a wide range of memory hierarchies.”
Find the technical paper link here (Physical Review Applied) or here (Research Gate, where you can request full text directly from the authors).
Rahul Mishra, Taehwan Kim, Jongsun Park, and Hyunsoo Yang
Phys. Rev. Applied 15, 024063 – Published 25 February 2021
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