The Changing IP Ecosystem

By Ann Mutschler - 21 Aug, 2014 - Comments: 0

Is a larger [getkc id="43" kc_name="IP"] company better suited to deliver what users need – from hardware to software to PDKs and reference designs – with larger and more diverse teams to draw upon, as well as deep foundry relationships? Or does it pay to small, quick and nimble? The answer to that question appears to be playing out in real time. As design complexity has increased, so ha... » read more

More Than Moore

By Ed Sperling - 21 Aug, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at Open-Silicon; Patrick Soheili, vice president and general manager of IP Solutions at eSilicon; Brandon Wang, engineering group director at Cadence; John Ferguson, product manager for DRC applications at Mentor Graphics; and Kevin Kranen, d... » read more

Executive Insight: Jack Harding

By Ed Sperling - 18 Aug, 2014 - Comments: 0

SE: What’s worrying you these days? Harding: One thing that bothers me is the cost of chip development on a per-chip basis. We seduce ourselves into thinking everything is wonderful because the cost per transistor is dropping in chunks. Gate costs are going down at every node. If you look at the secular trend, we’ve done a pretty good job putting a lot of stuff in a small space. In my bu... » read more

The Week In Review

By Ed Sperling - 15 Aug, 2014 - Comments: 0

Applied Materials announced its fiscal Q3 results. Net sales for the quarter were $2.27 billion compared with $1.98 billion in the same period in 2013, a 15% increase. Net income was $301 million for the period, compared with $168 million in 2013. On a non-GAAP basis, net income was $349 million, compared with $222 million in Q3 2013. The company expects fiscal Q4 net sales to be flat, plus or ... » read more

Signoff Intensity On The Rise

By The SE Staff - 15 Aug, 2014 - Comments: 2

By Ann Steffora Mutschler and Ed Sperling Lithography and signoff are crossing swords at 16/14nm and 10nm, creating new problems that raise questions about just how confident design teams will be when they sign off before tapeout — and how many respins are likely to follow. While designs at 20nm, 16nm and 14nm typically rely on colorless double patterning, at 10nm colors are mandatory. ... » read more

What’s Next For Memory?

By Mark LaPedus - 14 Aug, 2014 - Comments: 4

Apple, Samsung and others are developing the next wave of smartphones and tablets. OEMs want to integrate new memory schemes that provide more bandwidth at lower power. But there are some challenges in the arena that are prompting memory makers to rethink their mobile DRAM roadmaps. The conventional wisdom was that memory makers would ship mobile DRAMs based on the new LPDDR4 interface stand... » read more

Why The Next Couple Process Nodes Are So Critical

By Ed Sperling - 14 Aug, 2014 - Comments: 0

In the greater scheme of things, one process node doesn't matter all that much. In fact, it has become common practice for big chipmakers to skip nodes for some of their chips as power issues becoming increasingly complex, time-to-market windows shrink and leapfrogging is viewed as a way to maximize resources while remaining über-competitive. But the next process node, and certainly the nex... » read more

FinFET Ramp: Changing Market Dynamics?

By Joanne Itow - 14 Aug, 2014 - Comments: 1

Rolling out a new semiconductor technology always has its share of challenges, but it seems like the 14nm finFET process node is starting off with more than its share of delays and speculation. This week Intel revealed some of the details for its new microarchitecture, Broadwell, and their first product, the Intel Core M processor, to be manufactured using their second-generation finFET, 14... » read more

Pattern Matching: Blueprints For Further Success

By Mentor, a Siemens Business - 14 Aug, 2014 - Comments: 0

Design patterns have a wide variety of applications in the design, verification and test flows of IC development. From significantly reducing rule deck complexity to simplifying the task of avoiding known yield detractors to enhancing workflows such as design rule waiver recognition, pattern matching has become a useful tool throughout design, verification, and test process. Learn how Calibre P... » read more

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