tag: 2.5D

Noise Abatement
By Brian Bailey - 12 Oct, 2017 - Comments: 0

[getkc id="285" kc_name="Noise"] is a fact of life. Almost everything we do creates noise as a by-product and quite often what is a signal to one party is noise to another. Noise cannot be eliminated. It must be managed. But is noise becoming a larger issue in chips as the technology nodes get smaller and packaging becomes more complex? For some, the answer is a very strong yes, while for ot... » read more

The Chiplet Option
By Ed Sperling - 09 Oct, 2017 - Comments: 0

All of the leading chipmakers, foundries and OSATs are now working with some sort of advanced packaging. The next step is to add some consistency to those efforts to be able to assemble chips much more quickly and inexpensively. DARPA has been promoting chiplets as the best way to solve this problem, and for the military, this is a pretty logical choice. With a push toward heterogeneity in c... » read more

Advanced Packaging’s Progress
By Mark LaPedus - 09 Oct, 2017 - Comments: 0

Shim Il Kwon, CTO at STATS ChipPAC, sat down with Semiconductor Engineering to discuss the current and future trends of chip packaging. What follows are excerpts of that conversation. SE: The outsourced semiconductor assembly and test (OSAT) vendors provide third-party IC-packaging and test services. What are the big challenges for OSATs today? Shim: The OSAT market is very competitive, w... » read more

Plugging Gaps In Advanced Packaging
By Ann Mutschler - 27 Sep, 2017 - Comments: 0

The growing difficulty of cramming more features into an SoC is driving the entire chip industry to consider new packaging options, whether that is a more complex, integrated SoC or some type of advanced packaging that includes multiple chips. Most of the work done in this area so far has been highly customized. But as advanced packaging heads into the mainstream, gaps are beginning to appea... » read more

Light In A Package
By Ed Sperling - 18 Sep, 2017 - Comments: 1

Silicon photonics is gaining significant traction inside the data center, but creating a simpler method of packaging the laser with other circuitry remains a stumbling block for cutting costs and using this technology across a wider swath of applications. Progress does appear to be on the horizon, even though exact time frames remain unclear. The advantages of light in communications are wel... » read more

Multi-Physics Combats Commoditization
By Brian Bailey - 14 Sep, 2017 - Comments: 0

The semiconductor industry has benefited greatly from developments around digital circuitry. Circuits have grown in size from a few logic gates in the 1980s to well over 1 billion today. In comparison, analog circuits have increased in size by a factor of 10. The primary reason is that digital logic managed to isolate many of the physical effects from functionality, and to provide abstractions ... » read more

Get Ready For In-Mold Electronics
By Jeff Dorsch - 11 Sep, 2017 - Comments: 1

Imagine inserting the electronics into a product without using a printed circuit board, a module, or even a system-in-package. That's the promise of in-mold electronics (IME), a technology that has been around for years, but which is just beginning to see wider adoption. The technology is related to conductive inks and transparent conductive films. The IME manufacturing process is said to pr... » read more

Executive Insight: Lip-Bu Tan
By Ed Sperling - 06 Sep, 2017 - Comments: 2

Semiconductor Engineering sat down with Lip-Bu Tan, president and CEO of [getentity id="22032" e_name="Cadence"], to discuss disruptions and changes in the semiconductor industry, from machine learning and advance packaging to tools and business. What follows are excerpts of that conversation. SE: What do you see as the next big thing? Tan: Unlike mobility or cell phones, or PCs before th... » read more

IP Biz Changes As Markets Fragment
By Ed Sperling - 22 Aug, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss IP protection, tracking and reuse with Srinath Anantharaman, CEO of [getentity id="22203" e_name="ClioSoft"]; Jeff Galloway, CTO of Silicon Creations; Marc Greenberg, group director of product marketing for [getentity id="22032" e_name="Cadence"]'s IP Group; and John Koeter, vice president of marketing for [getentity id="22035" e_name="Synopsys"]' S... » read more

Is Design Innovation Slowing?
By Brian Bailey - 10 Aug, 2017 - Comments: 0

Paul Teich, principal analyst for Tirias Research, gave a provocative talk at the recent DAC conference entitled, "Is Integration Leaving Less Room for Design Innovation?" The answer isn't as simple as the question might suggest. "Integration used to be a driver for increasing the functionality of silicon," Teich said. "Increasingly, it will be used to incorporate more features of an entire ... » read more

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