What’s Missing In Packaging

As heterogeneous combinations of chips are used for new applications, will they be reliable enough?


The growth of advanced packaging on the leading edge of design is inching backwards into older nodes. With most technology—tools, methodologies, materials and processes—this is business as usual. But in packaging, it’s both counterintuitive and potentially problematic.

The main reason that companies began investing in advanced packaging—OSATs, foundries, chipmakers such as Intel and Qualcomm, was that it was too hard and too expensive to continue device scaling, particularly for analog components. So rather than develop everything at the same process, the initial idea was that a 40 or 65nm SerDes could be put into the same package with finFET-based logic and connected using a high-speed interface such as an interposer or using a flip-chip approach.

Digital logic, in contrast, will continue to scale to 3nm and maybe even beyond. But even there, performance benefits of scaling are diminishing. Scaling allows for greater transistor density, but the wires used to carry signals are becoming so thin that RC delay is now a first-order problem. So is routing congestion, and contention for resources such as memory. In some cases, signals have to travel through meters of thin wire.

Advanced packaging can shorten that distance, and it can improve throughput by using bigger or more (or both) pipes to carry signals between various blocks. That also reduces the amount of energy required to drive signals, which in turn reduces the overall heat in a device and extends battery life.

The big downside to a variety of packaging schemes, whether it’s a fan-out or 2.5D or some other system-in-package, has been cost. This is why most of the advanced packaging so far has either been done in high-volume markets such as smartphones, or in price-insensitive markets such as networking. But as bridge technology begins to replace full-die interposers, and as OSATs, foundries and equipment vendors begin squeezing the costs out of advanced packaging, more companies have started looking at packaging as a way to reduce time-to-market even at older nodes, and there are various schemes such as chiplets to make that even easier.

Advanced packaging is starting to gain mindshare in new markets such as automotive, particularly with LiDAR, sensor fusion and hubs, as well as in medical and industrial, where smaller form factors or customization are required but volumes are not large enough to make sophisticated designs affordable. The growing interest in embedded FPGAs is an offshoot of this shift.

Not all of the pieces are in place yet, however. How these devices are going to be inspected, measured and fully tested—particularly as different components are added from different vendors—isn’t clear yet. With everything on a single die, tester leads are exposed and all components are accessible. But as more components are stacked vertically, existing approaches are no longer sufficient.

This is a difficult enough task on a complex SoC, and there have been some rather glaring examples of designs gone awry in mobile phones and other consumer devices. But as advanced packaging moves into safety-critical markets, as well as industrial applications where chips are expected to last 15 or 20 years, much more rigorous requirements for verification, testing, inspection, metrology and long-term reliability will be required. What’s needed is a road map forward, and at this point there are still gaps in that map and lots of exploration involving alternative routes.

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