New BEOL/MOL Breakthroughs?

By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

2.5D, ASICs Extend to 7nm

By Mark LaPedus - 13 Jun, 2017 - Comments: 2

The leading-edge foundry market is heating up. For example, GlobalFoundries, Intel, Samsung and TSMC have recently announced their new and respective processes. The new processes from vendors range anywhere from 10nm to 4nm, although the current battle is taking place at 10nm and/or 7nm. In fact, one vendor, GlobalFoundries, this week will describe more details about its previously-announced... » read more

What’s Next In Scaling, Stacking

By Mark LaPedus - 05 Jun, 2017 - Comments: 9

An Steegen, executive vice president of semiconductor technology and systems at [getentity id="22217" e_name="Imec"], sat down with Semiconductor Engineering to discuss IC scaling, chip stacking, packaging and other topics. Imec is an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Chipmakers are shipping 16nm/14nm processes with 10nm and 7nm technologies... » read more

Tech Talk: System In Package

By Ed Sperling - 05 Jun, 2017 - Comments: 0

ASE fellow and senior technical advisor William Chen talks about advanced packaging options and why they are now so important. » read more

High-Stakes Litho Game

By Ed Sperling - 18 May, 2017 - Comments: 0

The commercial introduction of EUV looks all but assured these days. There is enough history to show it works. Uptime and throughput are improving, and systems are shipping today. The question now is how to measure its success. In the short-term, this is a fairly simple financial exercise for companies like ASML and Zeiss, which have been closely collaborating to get these massive systems ou... » read more

Moore’s Law: Toward SW-Defined Hardware

By Ed Sperling - 15 May, 2017 - Comments: 2

Pushing to the next process node will continue to be a primary driver for some chips—CPUs, FPGAs and some ASICS—but for many applications that approach is becoming less relevant as a metric for progress. Behind this change is a transition from using customized software with generic hardware, to a mix of specialized, heterogeneous hardware that can achieve better performance with less ene... » read more

2.5D, Fan-Out Inspection Issues Grow

By Ed Sperling - 12 May, 2017 - Comments: 0

As advanced packaging moves into the mainstream, packaging houses and equipment makers are ratcheting up efforts to solve persistent metrology and inspection issues. The goal is to lower the cost of fan-outs, [getkc id="82" kc_name="2.5D"] and [getkc id="42" kc_name="3D-IC"], along with a number of other packaging variants consistent with the kinds of gains that are normally associated with Moo... » read more

Advanced Packaging Goes Mainstream

By Ed Sperling - 08 May, 2017 - Comments: 0

The roadmap for shrinking digital logic will continue for at least the next 10 years. For others devices, particularly analog, it will slow down or end. And therein lies one of the most fundamental changes in semiconductor design and manufacturing in the past half century. This is no longer just talk. Apple is using a fan-out architecture in its iPhone 7. Memory makers are stacking NAND and ... » read more

Ultra-Thin Substrate Assembly Challenges For Advanced Flip Chip Package

By STATS ChipPAC - 08 May, 2017 - Comments: 0

Advanced semiconductor packaging requirements for higher and faster performance in a thinner and smaller form factor continues to grow for mobile, network and consumer devices. While the increase in device input/output (I/O) count is driven by the famous “Moore’s Law”, the packaging industry is experiencing opposing trends for more complex packaging solutions while the expected cost targe... » read more

The Future of Testing

By Jeff Dorsch - 08 May, 2017 - Comments: 0

In our previous test blog posts, we looked at the history of automated test equipment for semiconductors and for printed circuit boards. This month, we look ahead to the test technologies that are emerging. The chip ATE field has essentially boiled down to Advantest, Teradyne, and Xcerra (LTX-Credence), while the board test market is dominated by Teradyne and Keysight Technologies (formerly ... » read more

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tag: 2.5D

New BEOL/MOL Breakthroughs?

2.5D, ASICs Extend to 7nm

What’s Next In Scaling, Stacking

Tech Talk: System In Package

High-Stakes Litho Game

Moore’s Law: Toward SW-Defined Hardware

2.5D, Fan-Out Inspection Issues Grow

Advanced Packaging Goes Mainstream

Ultra-Thin Substrate Assembly Challenges For Advanced Flip Chip Package

The Future of Testing

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