2.5D Timetable Coming Into Focus

By Ed Sperling - 23 Oct, 2014 - Comments: 0

After years of empty promises, the timetable for [getkc id="82" kc_name="2.5D"] is coming into better focus. Large and midsize chipmakers are behind it, real silicon is being developed, and contracts are being signed. That doesn't mean all of the pieces are in place or that market uptake is at the neck of the hockey stick. And it certainly doesn't mean the semiconductor industry is going to ... » read more

Why Is My Device Better Than Yours?

By Ed Sperling - 23 Oct, 2014 - Comments: 0

Differentiation is becoming a big problem in the semiconductor industry with far-reaching implications that extend well beyond just chips. The debate over the future of [getkc id="74" comment="Moore's Law"] is well known, but it's just one element in a growing list that will make it much harder for chip companies, IP vendors and even software developers to stand out from the pack. And withou... » read more

A New Reuse Paradigm To Take 2.5D Packaging Technology Mainstream

By Jeff Scott - 23 Oct, 2014 - Comments: 0

With all of the recent product implementations and demonstrations of the technical viability of 2.5D technology, there is a lot of excitement around its potential. However, as with any new technology, there are concerns with cost and risk that limit mainstream adoption. Cost reduction and risk mitigation require some level of volume production, and therein lies a classic Catch-22. Is there a wa... » read more

Litho Options Sparse After 10nm

By Mark LaPedus - 16 Oct, 2014 - Comments: 0

Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in [getkc id="80" comment="lithography"], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm. So now, chipmakers are focusing on the lithography options for 7nm. As before, the options include the usual suspects—[gettech id="... » read more

One-On-One: Mike Muller

By Ed Sperling - 13 Oct, 2014 - Comments: 0

SE: What happens with memory, where access is more localized? Muller: Hybrid memory cube is one approach. HBM is another. ARM is chairing an IEEE standards group for a next-gen memory interface to make sure we build memories that fit mobile as well as networking and classic servers. Whereas in the past, memories were driven from the performance, we need to make the power scales with the band... » read more

Memory Directions Uncertain

By Brian Bailey - 09 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down with a panel of experts to find out what is happening in world of memories. Taking part in the discussion are [getperson id="11073" comment="Charlie Cheng"], chief executive officer at [getentity id="22135" e_name="Kilopass Technology"]; Navraj Nandra, senior director of marketing for Analog/Mixed signal IP, embedded memories and logic libraries at [getentity ... » read more

Multi-Die Packaging Gains Steam

By Si2 - 06 Oct, 2014 - Comments: 0

By Herb Reiter Many readers will be familiar with my extensive background and focus in the emerging field of 3D IC technology, including both 3D stacked die and 2.5 interposer design flows. Now, I am excited to bring my expertise and passion to Silicon Integration Initiative (Si2), where I am now Director of 3D Programs, helping Si2’s members in the Open3D Technical Advisory Board develop pr... » read more

More Than Moore

By Ed Sperling - 01 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

Which Comes First?

By Ed Sperling - 25 Sep, 2014 - Comments: 0

Methodologies in IC design typically follow tools. The tools enable the methodologies, and chipmakers' businesses are built around both of them. That has been the rock-solid foundation for the design and production of chips since well before the impenetrable 1-micron wall. But that approach is falling apart at 28nm, and it will continue to crumble at 16/14nm and 10nm. It simply isn't fast en... » read more

Why Multi-Die Integration Really Is On Its Way

By Steve Schulz - 19 Sep, 2014 - Comments: 0

Admit it. You’ve heard a lot about 3D IC’s for years now, and it’s starting to get old. Lots of talk but not much action, you say? Maybe it will never happen, you say? Well, perhaps it’s time to reassess the current situation, reevaluate emerging needs, and reset our “3D” paradigm for the coming multi-die imperative. The problems associated with 3D IC (stacked die) are real and v... » read more

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tag: 2.5D

2.5D Timetable Coming Into Focus

Why Is My Device Better Than Yours?

A New Reuse Paradigm To Take 2.5D Packaging Technology Mainstream

Litho Options Sparse After 10nm

One-On-One: Mike Muller

Memory Directions Uncertain

Multi-Die Packaging Gains Steam

More Than Moore

Which Comes First?

Why Multi-Die Integration Really Is On Its Way

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