tag: 3D-IC

Using Deep Data For Improved Reliability Testing
By Ed Sperling - 08 Jan, 2024 - Comments: 0

Reliability testing always has been a challenge for semiconductor companies, but it’s becoming much more difficult as devices continue to shrink, as they’re integrated together in advanced packages, and as they’re utilized under different conditions with life expectancy that varies by application and use case. Nir Sever, senior director of business development at proteanTecs, and Luca Mor... » read more

System-Driven PPA For Multi-Chiplet Designs
By Cadence - 20 Dec, 2023 - Comments: 0

As we approach the device scaling limitations at advanced nodes, the demand on compute performance and data transfer for hyperscale data center and AI designs is at an all-time high. Advanced systems-on-chip (SoCs) are reaching reticle size limits, and there has been a need to find innovative solutions to continue Moore’s law scaling and achieve performance improvements with reduced power. St... » read more

Next-Gen Power Integrity Challenges
By Ed Sperling - 14 Dec, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss power integrity challenges and best practices in designs at 7nm and below, and in 2.5D and 3D-IC packages, with Chip Stratakos, partner, physical design at Microsoft; Mohit Jain, principal engineer at Qualcomm; Thomas Quan, director at TSMC; and Murat Becer, vice president at Ansys. What follows are excerpts of that conversatio... » read more

Improving AI Productivity With AI
By Ed Sperling - 28 Nov, 2023 - Comments: 0

AI is showing up or proposed for nearly all aspects of chip design, but it also can be used to improve the performance of AI chips and to make engineers more productive earlier in the design process. Matt Graham, product management group director at Cadence, talks with Semiconductor Engineering about the role of AI in identifying patterns that are too complex for the human brain to grasp, how t... » read more

Thermal Warpage Simulation Of A Temperature-Dependent Linear Elastic Material Package
By Cadence - 08 Nov, 2023 - Comments: 0

The shift to advanced packaging in 3D and 2.5D IC design is making the numerical analysis of thermal warpage in electronic devices a crucial part of the design process. A reliable numerical tool enables the designer to perform early design analysis that accurately predicts warpage, thereby shortening the design process. The Cadence Celsius Thermal Solver integrated within the Cadence IC, pac... » read more

Anatomy Of A System Simulation
By Brian Bailey - 26 Oct, 2023 - Comments: 0

The semiconductor industry has greatly simplified analysis by consolidating around a small number of models and abstractions, but that capability is breaking down both at the implementation level and at the system level. Today, the biggest pressure is coming from the systems industry, where the electronic content is a small fraction of what must be integrated together. Systems companies tend... » read more

Making Connections In 3D Heterogeneous Integration
By Ann Mutschler - 26 Oct, 2023 - Comments: 0

Activity around 3D heterogeneous integration (3DHI) is heating up, driven by growing support from governments, the need to add more features and compute elements into systems, and a widespread recognition that there are better paths forward than packing everything into a single SoC at the same process node. The leading edge of chip design has changed dramatically over the last few years. Int... » read more

Everyone’s A System Designer With Heterogeneous Integration
By Ann Mutschler - 02 Oct, 2023 - Comments: 0

The move away from monolithic SoCs to heterogeneous chips and chiplets in a package is accelerating, setting in motion a broad shift in methodologies, collaborations, and design goals that are felt by engineers at every step of the flow, from design through manufacturing. Nearly every engineer is now working or touching some technology, process, or methodology that is new. And they are inter... » read more

Why Chiplets Don’t Work For All Designs
By Ed Sperling - 20 Sep, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss use cases and challenges for commercial chiplets with Saif Alam, vice president of engineering at Movellus; Tony Mastroianni, advanced packaging solutions director at Siemens Digital Industries Software; Mark Kuemerle, vice president of technology at Marvell; and Craig Bishop, CTO at Deca Technologies. What follows are excerpts... » read more

Distributed Batteries Within A Heterogeneous 3D IC To Optimize Performance
By Technical Paper Link - 28 Aug, 2023 - Comments: 0

A technical paper titled “On-Chip Batteries as Distributed Energy Sources in Heterogeneous 2.5D/3D Integrated Circuits” was published by researchers at University of Florida and Brookhaven National Laboratory. Abstract: "Energy efficiency in digital systems faces challenges due to the constraints imposed by small-scale transistors. Moreover, the growing demand for portable consumer electr... » read more

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