First Forays Into True 3D-IC Designs


Experts at the Table: Semiconductor Engineering sat down to discuss initial forays into 3D-ICs and what problems early adopters will encounter, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager... » read more

Mitigating Warpage In Multi-Chiplet Systems


Warpage of dies, redistribution layers, and interposers is a growing problem in multi-chiplet packages, and it can have a dramatic impact on the behavior and reliability of these devices. Multiple factors contribute to warpage, including larger chip sizes, severe thinning of the silicon substrate, temporary bonding and debonding processes, and scaling of bump pitch and size. Each of these ca... » read more

Navigating Reliability Potholes: Early 3D Stress Analysis For Automotive ICs


The rise of 3D integrated circuits (ICs) and heterogeneous packaging is reshaping how automotive ICs fulfill demanding analog and sensor requirements. Whether for radar, lidar, sensor fusion or domain controllers, advanced packaging enables new levels of integration—and performance—in automotive electronics. Yet, as these architectures grow more complex, they also introduce new forms of mec... » read more

3D-ICs In The Automotive Market: Breaking Barriers With AI-Driven EDA Tools


The automotive industry is experiencing a significant transformation as it adopts innovations like autonomous driving technologies and ultra-connected ecosystems. At the core of this change is a rising demand for compact, high-performance semiconductor solutions that can handle the increasing complexity of modern vehicle architecture. One promising development is three-dimensional integrated ci... » read more

Calibre 3DStress: Advanced Stress Analysis For Reliable 3D IC Design


As the industry transitions toward advanced 3D IC architectures and heterogeneous integration, managing thermo-mechanical stress is essential for product quality and long-term reliability. Calibre 3DStress enables design and packaging teams to simulate, analyze and disposition stresses imparted on the chip during or after the packaging process, ensuring that potential failure risks—such as wa... » read more

Chiplet Interfaces Embrace Failures


Redundancy in chiplet interfaces is now a prerequisite for achieving sufficient yield in high-performance computing devices, which today are packed with tens of thousands of interconnects. And as the number and density of those interconnects increases, the prospects for yield only worsen. For more than two decades, high-speed I/O interfaces have included reliability strategies to manage in-f... » read more

3DICs: Atomic-Scale Behavior of Electromigration in Cu−Cu Joints (NYCU, ITRI)


A new technical paper titled "In Situ Atomic-Scale Investigation of Electromigration Behavior in Cu–Cu Joints at High Current Density" was published by researchers at National Yang Ming Chiao Tung University (NYCU) and the Industrial Technology Research Institute (ITRI). Excerpt "Electromigration (EM) poses significant challenges to the reliability of miniaturized devices, particularly th... » read more

Can Today’s Processor Architectures Be More Efficient?


For years, processors focused on performance, and that performance had little accountability to anything else. Performance still matters, but now it must be accountable to power. If small gains in performance result in disproportionate power gains, designers may need to discard such improvements in favor of more power-efficient ones. Although current architectures undergo a steady cadence of... » read more

Co-Packaged Optics Reaches Power Efficiency Tipping Point


Commercialization has started for network switches based on co-packaged optics (CPO), which are capable of routing signals at terabits per second speeds, but manufacturing challenges remain regarding fiber-to-photonic IC alignment, thermal mitigation, and optical testing strategies. By moving the optical-to-electronic data conversion as close as possible to the GPU/ASIC switch in data center... » read more

Executive Outlook: Chiplets, 3D-ICs, and AI


Semiconductor Engineering sat down to discuss chiplets and the challenges of moving to 3D-ICs with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadence; Anand Thiruvengadam, senior director and head of AI product ... » read more

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