tag: 3D ICs

Blog Review: April 4
By Jesse Allen - 04 Apr, 2018 - Comments: 0

Synopsys' Richard Solomon explains PCIe's upstream and downstream component naming and why understanding the perspective is key. Mentor's Cristian Filip dives into frequency domain analysis for high data rate SerDes links and the movement toward a simpler way of channel characterization. Cadence's Paul McLellan takes a look at the history of the RISC processors and the death of microcode ... » read more

Blog Review: Dec. 2
By Jesse Allen - 02 Dec, 2015 - Comments: 0

To celebrate ARM's 25th birthday, Neil Cooper teamed up with the Science Museum in London to feature 25 people or objects that were pivotal to the creation of modern technology. This week: James Clerk Maxwell and Heinrich Hertz. Ansys' Bill Vandermark delves deep into the oceans with energy-storing balloons and up to the sky on a diamond thread in his top technology and engineering articles ... » read more

The Week In Review: Design
By Ed Sperling - 04 Apr, 2014 - Comments: 0

Tools Mentor Graphics rolled out a new platform for verification of unknown voltage levels (Xs) at the register transfer and gate levels, fusing together simulation and formal verification under one umbrella. The company says the approach will limit bugs and wasted effort caused by X-optimism and pessimism. Jasper Design Automation unveiled a new tool to verify the sequential functional equ... » read more

Plug-And-Play Test Strategy For 3D ICs
By Various Writers - 26 Feb, 2014 - Comments: 0

As the industry transitions to 3D ICs, new test strategies are being developed to meet to two 3D IC test goals: improving the pre-packaged test quality and establishing new tests between the stacked die. Solutions for 3D IC test are developing rapidly and are based on mature technologies. In this paper, we describe a test strategy for 3D ICs based on a plug-and-play architecture that allows die... » read more

Many Stresses Impact TSVs
By Ann Mutschler - 20 Feb, 2014 - Comments: 0

Too much stress in humans is typically not beneficial, and the same goes for 3D-ICs with through-silicon vias (TSVs). Stress effects here come from the fact that copper, which is the conductor of choice for the TSVs, and silicon have different coefficients of thermal expansion. “If you can imagine that a via will be etched through the silicon, copper will be deposited inside and then t... » read more

What Just Happened?
By Brian Fuller - 12 Dec, 2013 - Comments: 0

Boy that went by fast. One minute, I’m waking up a little groggy on New Year’s Day, wondering whether the silicon industry is ever going to rebound. The next minute, it’s today and the industry had a good year, and is, in many ways, a completely different animal than it was 12 months ago. Innovation is evolutionary, sure. But if you really think about 2013, you can make an argument tha... » read more

The “Last Simple Node” And the Internet of Things
By Brian Fuller - 17 Oct, 2013 - Comments: 0

Power, performance and size are key targets that will enable the expected explosion of the Internet of Things (IoT). Today, most observers see the path to that running directly through 16/14nm finFET and below for the node’s ability to manage power and size and boost integration. Geoff Lees isn’t your average observer. The vice president and general manager of Freescale’s microcon... » read more

Fundamentals For 3D IC Flows
By Ann Mutschler - 05 Apr, 2012 - Comments: 0

While true 3D ICs are a few years off, 2.5D is here. There are some key differences, namely that with 2.5D the interposer is a passive die, but there also are some fundamental shared requirements. Samta Bansal, senior product marketing for Silicon Realization at Cadence asserted that first, the digital, custom and package environments must be seamless. “There has to be a co-design between ... » read more

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