tag: 3nm

Some Chipmakers Sidestep Scaling, Others Hedge
By Ed Sperling - 15 Nov, 2018 - Comments: 0

The rising cost of developing chips at 7nm coupled with the reduced benefits of scaling have pried open the floodgates for a variety of options involving new materials, architectures and packaging that either were ignored or not fully developed in the past. Some of these approaches are closely tied to new markets, such as assisted and autonomous vehicles, robotics and 5G. Others involve new ... » read more

Accelerators Everywhere. Now What?
By Ed Sperling - 08 Nov, 2018 - Comments: 0

It's a good time to be a data scientist, but it's about to become much more challenging for software and hardware engineers. Understanding the different types and how data flows is the next path forward in system design. As the number of sources of data rises, creating exponential spikes in the volume of data, entirely new approaches to computing will be required. The problem is understandi... » read more

Using DSA With EUV
By Ed Sperling - 05 Nov, 2018 - Comments: 1

James Lamb, deputy CTO for advanced semiconductor manufacturing and corporate technical fellow at Brewer Science, looks at how directed self-assembly can be used to supplement EUV at advanced nodes. https://youtu.be/PItF4egHOxc     See other tech talk videos here » read more

EUV’s Uncertain Future
By Ed Sperling - 18 Oct, 2018 - Comments: 8

The ground appears to be solidifying under EUV. Intel announced this week it is reducing its stake in ASML to less than 3%, the second such move in a year. Apparently ASML no longer needs outside help. According to the company's earnings report, ASML turned in net sales of €2.776 billion, a slight increase over the €2.447 billion (GAAP) the company reported in Q3 and way up over the €... » read more

GF Puts 7nm On Hold
By Mark LaPedus - 27 Aug, 2018 - Comments: 6

GlobalFoundries is putting its 7nm finFET program on hold indefinitely and has dropped plans to pursue technology nodes beyond 7nm. The moves, which mark a major shift in direction for the foundry, involve a headcount reduction of about 5% of its worldwide workforce. At the same time, the company is also moving its ASIC business into a new subsidiary. As a result of GlobalFoundries’ ann... » read more

Week In Review: Design, Low Power
By Jesse Allen - 17 Aug, 2018 - Comments: 0

Intel disclosed a speculative execution side-channel attack method called L1 Terminal Fault (L1TF). Leslie Culbertson, Intel's executive vice president and general manager of Product Assurance and Security, writes: "This method affects select microprocessor products supporting Intel Software Guard Extensions (Intel SGX) and was first reported to us by researchers at KU Leuven University, Techni... » read more

More Performance At The Edge
By Ed Sperling - 09 Aug, 2018 - Comments: 0

Shrinking features has been a relatively inexpensive way to improve performance and, at least for the past few decades, to lower power. While device scaling will continue all the way to 3nm and maybe even further, it will happen at a slower pace. Alongside of that scaling, though, there are different approaches on tap to ratchet up performance even with chips developed at older nodes. This i... » read more

Scaling Sideways
By Ed Sperling - 19 Jul, 2018 - Comments: 0

The next steps in semiconductor technology don't follow the same vectors. While 3nm chips are likely to roll out at some point in the future, it's not clear what the business case will be for developing them. What's clear is the number of companies developing chips at that node will shrink to a handful (or less), because they're going to be far too expensive to design, verify and manufacture... » read more

5nm Design Progress
By Ann Mutschler - 17 Jul, 2018 - Comments: 1

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

Where Is Selective Deposition?
By Mark LaPedus - 25 Jun, 2018 - Comments: 4

For years, the industry has been working on an advanced technology called area-selective deposition for chip production at 5nm and beyond. Area-selective deposition, an advanced self-aligned patterning technique, is still in R&D amid a slew of challenges with the technology. But the more advanced forms of technology are beginning to make some progress, possibly inching closer from the la... » read more

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