tag: 5nm

The Next 5 Years Of Chip Technology
By Ed Sperling - 18 Dec, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of [getentity id="22820" comment="Lam Research"]; Mark Dougherty, vice president of advanced module engineering at [getentity id="22819" comment="GlobalFoundries"]; David Shortt, technical fellow at [getentity id="22876" co... » read more

Noise At 7nm And Beyond
By Ed Sperling - 14 Dec, 2017 - Comments: 0

The digital and analog worlds always have been very different. Digital engineers see the world in terms of electrons and a well-defined set of numerical values. Their waves are discrete and squared off and their devices are often noisy when they turn on and off. Analog engineers think in terms of quiet, smooth waves, and they are very concerned about anything that can disrupt those waves, such ... » read more

Big Challenges, Changes For Debug
By Ann Mutschler - 04 Dec, 2017 - Comments: 1

By Ann Steffora Mutschler & Ed Sperling Debugging a chip always has been difficult, but the problem is getting worse at 7nm and 5nm. The number of corner cases is exploding as complexity rises, and some bugs are not even on anyone's radar until well after devices are already in use by end customers. An estimated 39% of verification engineering time is spent on debugging activities the... » read more

What’s Next For Atomic Layer Etch?
By Mark LaPedus - 16 Nov, 2017 - Comments: 0

After years in R&D, several fab tool vendors last year finally began to ship systems based a next-generation technology called atomic layer etch (ALE). [getkc id="284" kc_name="ALE"] is is moving into 16/14nm, but it will play a big role at 10/7nm and beyond. The industry also is working on the next wave of ALE technology for advanced logic and memory production. Used by chipmakers fo... » read more

Overlay Challenges On The Rise
By Mark LaPedus - 16 Nov, 2017 - Comments: 2

The overlay metrology equipment market is heating up at advanced nodes as the number of masking layers grows and the size of the features that need to be aligned continue to shrink. Both ASML and KLA-Tencor recently introduced new [getkc id="307" kc_name="overlay"] metrology systems, seeking to address the increasing precision required for lines, cuts and other features on each layer. At 10/... » read more

Lots Of Little Knobs For Power
By Ann Mutschler - 09 Nov, 2017 - Comments: 3

Dynamic power is becoming a much bigger worry at new nodes as more finFETs are packed on a die and wires shrink to the point where resistance and capacitance become first-order effects. Chipmakers began seeing dynamic power density issues with the first generation of [getkc id="185" kc_name="finFETs"]. While the 3D transistor structures reduced leakage current by providing better gate contro... » read more

Searching For EUV Mask Defects
By Mark LaPedus - 19 Oct, 2017 - Comments: 2

Chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, but several challenges need to be solved before this technology can be used in production. One lingering issue that is becoming more worrisome is how to find [gettech id="31045" comment="EUV"] mask defects. That isn't the only issue, of course. The industry continues to work on the power source and resists. Bu... » read more

Next-Gen Mask Writer Race Begins
By Mark LaPedus - 19 Oct, 2017 - Comments: 5

Competition is heating up in the mask writer equipment business as two vendors—Intel/IMS and NuFlare—vie for position in the new and emerging multi-beam tool segment. Last year, Intel surprised the industry by acquiring IMS Nanofabrication, a multi-beam e-beam mask writer equipment vendor. Also last year, IMS, now part of Intel, began shipping the world’s first multi-beam mask writer f... » read more

New Power Concerns At 10/7nm
By Ann Mutschler - 16 Oct, 2017 - Comments: 1

As chip sizes and complexity continues to grow exponentially at 7nm and below, managing power is becoming much more difficult. There are a number of factors that come into play at advanced nodes, including more and different types of processors, more chip-package decisions, and more susceptibility to noise of all sorts due to thinner insulation layers and wires. The result is that engineers ... » read more

Advanced Packaging’s Progress
By Mark LaPedus - 09 Oct, 2017 - Comments: 0

Shim Il Kwon, CTO at STATS ChipPAC, sat down with Semiconductor Engineering to discuss the current and future trends of chip packaging. What follows are excerpts of that conversation. SE: The outsourced semiconductor assembly and test (OSAT) vendors provide third-party IC-packaging and test services. What are the big challenges for OSATs today? Shim: The OSAT market is very competitive, w... » read more

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