tag: 5nm

Looming Issues And Tradeoffs For EUV
By Mark LaPedus - 25 Sep, 2017 - Comments: 5

Momentum is building for extreme ultraviolet (EUV) lithography, but there are still some major challenges to solve before this long-overdue technology can be used for mass production. [gettech id="31045" comment="EUV"] lithography—a next-generation technology that patterns tiny features on a chip—was supposed to move into production around 2012. But over the years, EUV has encountered se... » read more

The Materials Gap
By Ed Sperling - 21 Sep, 2017 - Comments: 0

When consolidation thinned the ranks of semiconductor foundries and equipment makers, materials companies figured things were about to get better. They haven't. There are a couple of reasons for this. First, semiconductors are now so complex and difficult to develop that a slew of innovations are required on all sides. Everyone is familiar with transistor structures, interconnects and lithog... » read more

Unsolved Litho Issues At 7nm
By Ed Sperling - 21 Sep, 2017 - Comments: 1

By Ed Sperling & Mark LaPedus EUV lithography is creating a new set of challenges on the photomask side for which there currently are no simple solutions. While lithography is viewed as a single technology, [gettech id="31045" comment="EUV"] actually is a collection of technologies. Not all of those technologies have advanced equally and simultaneously, however. For example, aberrations... » read more

Node Warfare?
By Mark LaPedus - 20 Sep, 2017 - Comments: 6

By Mark LaPedus & Ed Sperling GlobalFoundries uncorked a 12nm finFET process, which the company said will provide a 15% increase in density and more than 10% improvement in performance over the foundry's existing 14nm process. This is GlobalFoundries' second 12nm process. It announced a 12nm FD-SOI process called 12FDX last September, although it first mentioned a 12nm process back in J... » read more

Ruthenium Liners Give Way To Ruthenium Lines
By Katherine Derbyshire - 17 Aug, 2017 - Comments: 0

For several years now, integrated circuit manufacturers have been investigating alternative barrier layer materials for copper interconnects. As interconnect dimensions shrink, the barrier accounts for an increasing fraction of the total line volume. As previously reported, both cobalt and ruthenium have drawn substantial interest because they can serve as both barrier and seed layers, minimizi... » read more

What’s After FinFETs?
By Mark LaPedus - 24 Jul, 2017 - Comments: 3

Chipmakers are readying their next-generation technologies based on 10nm and/or 7nm finFETs, but it's still not clear how long the finFET will last, how long the 10nm and 7nm nodes for high-end devices will be extended, and what comes next. The industry faces a multitude of uncertainties and challenges at 5nm, 3nm and beyond. Even today, traditional chip scaling continues to slow as process ... » read more

Is 7nm The Last Major Node?
By Ed Sperling - 20 Jul, 2017 - Comments: 3

A growing number of design and manufacturing issues are prompting questions about what scaling will really look like beyond 10/7nm, how many companies will be involved, and which markets they will address. At the very least, node migrations will go horizontally before proceeding numerically. There are expected to be more significant improvements at 7nm than at any previous node, so rather th... » read more

Shrink Or Package?
By Ed Sperling - 19 Jun, 2017 - Comments: 0

Advanced packaging is rapidly becoming a mainstream option for chipmakers as the cost of integrating heterogeneous components on a single die continues to rise. Despite several years of buzz around this shift, the reality is that it has taken more than a half-century to materialize. Advanced [getkc id="27" kc_name="packaging"] began with IBM flip chips in the 1960s, and it got another boost ... » read more

Inside Chip R&D
By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss R&D challenges, EUV and other topics with Luc Van den hove, president and chief executive of Imec, an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Clearly, Moore’s Law is slowing down. The traditional process cadence is extending from 2 years to roughly 2.5 to 3 years. Yet, R&D is not slowing down, right? ... » read more

New BEOL/MOL Breakthroughs?
By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

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