Inside Chip R&D

Imec CEO discusses R&D challenges, EUV and chips.


Semiconductor Engineering sat down to discuss R&D challenges, EUV and other topics with Luc Van den hove, president and chief executive of Imec, an R&D organization in Belgium. What follows are excerpts of that conversation.

SE: Clearly, Moore’s Law is slowing down. The traditional process cadence is extending from 2 years to roughly 2.5 to 3 years. Yet, R&D is not slowing down, right?

Van den hove: We all realize it’s not getting easier. So, in terms of research, we really have to further accelerate it. To continue Moore’s Law, there are some phenomenal challenges. EUV has been one of those big challenges. It’s only because of the hard work and extreme dedication that it comes now to a point where it’s going to enter manufacturing. The same is with the device structures. We can only keep Moore’s Law alive by investing enormously into the innovation and research part.

SE: As a result, it costs more time and money to do R&D. Yet, companies may not have the resources to do everything in R&D. This in turn benefits and propels dedicated R&D organizations like Imec, right?

Van den hove: Absolutely. Imec has been growing every year. In terms of partnerships, we are continuing to grow. We are getting stronger commitments from virtually all parts of the value chain. We are getting very strong commitments from all of the suppliers. The suppliers have a challenge. As everything gets more expensive and difficult, they have a challenge to develop all of these technologies. Certainly, in their own development facilities, their internal process capabilities are limited. That’s where Imec has become kind of a central hub, where they come and have their most advanced capabilities and tools. They can make use of Imec’s pilot line to demonstrate their own capabilities. That has become a popular model.

SE: What else?

Van den hove: This is not only for the equipment suppliers, but also the materials suppliers. A lot of innovation comes from the materials. For example, there are metal-containing resists for EUV. Inpria, for example, is developing this technology. Inpria is a startup. They would never be able to invest in an EUV scanner. So, we would enable all of these new initiatives and test out all of these new concepts.

SE: Imec has been working with leading-edge chipmakers equipment vendors for years. What’s new here?

Van den hove: We are seeing activity up in the value chain towards the fabless companies. We are seeing strong and growing commitments from them. We are also expanding into several domains like the IoT space, health care devices and smart city applications. So we are moving up the value chain there. We are doing that by setting up more partnerships in those areas. We are also making sure that we have a good R&D base there.

SE: Last year, Imec merged with another R&D organization. What was that about?

Van den hove: That’s where the merger of iMinds came in. In this merger, we added a lot of skills in terms of data science capability, artificial intelligence and security-related topics.

SE: Attracting new engineering talent is very difficult in the semiconductor industry. This is especially true in the United States and elsewhere. Is Imec seeing the same trend?

Van den hove: We are actually doing very well in that respect. We are successful in attracting young people in our model. We have very strategic partnerships with all of the universities locally. We have partnerships internationally. We basically have hundreds of PhD students who do their research projects at Imec. They obtain their degrees from the university. This is the ideal way to select the best people and try to convince them to stay. We continuously add new people.

SE: It’s difficult to get students interested in math and science in the United States. What about Europe?

Van den hove: It is a challenge in Europe. But in the region here, we are successful and we’ve really turned the trend. The number of young people starting in engineering and science has increased. Overall, there is a renewed interest in science and engineering here.

SE: Let’s go back to extreme ultraviolet (EUV) lithography. You mentioned EUV resists. There are some challenges here, right?

Van den hove: Clearly, there are two paths. There are the chemically-amplified resists and metal-containing resists. Both are making very good progress. Today, I wouldn’t choose one over the other. It’s good to have two options. They are pretty equal in performance. Of course, metal-containing resists do have the worry of potential metal contamination in the circuits. But that’s a point we are investigating in detail. The chemically-amplified resists are performing very well today. One of the questions is how scalable is that technology in terms of when you go to higher resolutions. There are questions whether the dose can be reduced enough. That’s where metal-containing resists come in.

SE: What about the EUV source?

Van den hove: It continues to improve in terms of power. But even more importantly, it is improving in terms of reliability. The combination of both is important and there is progress on both sides.

SE: What else can you say about EUV?

Van den hove: Now, the maturity has really reached a level where several companies are now committing to it.

SE: Let’s move to the transistor. It appears that finFETs may extend to 5nm. Then, people are talking about gate-all-around FETs, sometimes called the lateral nanowire FET. Another variant is called the nanosheet FET. Beyond that, there are a range of options. It’s hard to predict which one will be the winner. How do you narrow the options?

Van den hove: Our role is to narrow the options and to assess the advantages and disadvantages of the various scenarios. Then, it’s up to our partners to make a final selection, of course. Our task is to make assessments and kind of pre-select I would say. We do that with modeling and also generating real data on advanced devices.

SE: How do you see this playing out?

Van den hove: We think the finFET will be extendable to something like the 5nm node. Then, the horizontal nanowires are going to be one of the very likely candidates, probably also with some silicon germanium and germanium channels. Then, beyond 3nm, there are still a lot of options. One option is the stacked nanowire, where we have n and p channels on top of each other, like CFET or complementary FET. Or, there could be vertical nanowires. But that’s another major change. We are assessing both options. It’s too early to make a conclusion here.

Related Stories
Uncertainty Grows For 5nm, 3nm
Nanosheets and nanowire FETs under development, but costs are skyrocketing. New packaging options could provide an alternative.
Why EUV Is So Difficult
One of the most complex technologies ever developed is getting closer to rollout. Here’s why it took so long, and why it still isn’t a sure thing.
What’s Next In Scaling, Stacking
The 40nm gate-pitch cliff, 3D SoCs with microfluidic cooling, new fan-outs and 2.5D—it’s all on the table.


memister says:

If they are committing to EUV in spite of data or analysis which is really against it, they are not doing technology but trying to fulfill some technopolitical agenda. Otherwise, there shouldn’t be an endorsement when it doesn’t make sense. Reducing doses, in the face of stochastics?

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