tag: 5nm

What Happened To Next-Gen Lithography?
By Mark LaPedus - 03 Sep, 2014 - Comments: 2

Chipmakers continue to march down the process technology curve. Using today’s optical lithography and multiple patterning, the semiconductor industry is scaling its leading-edge devices far beyond what was once considered possible. The question is how far can the industry extend 193nm immersion [getkc id="80" comment="lithography"] and multiple patterning before these technologies become t... » read more

More Problems Ahead
By Ed Sperling - 25 Aug, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss future scaling problems with Lars Liebmann, a fellow at IBM; Adam Brand, managing director of transistor technology at Applied Materials; Karim Arabi, vice president of engineering at Qualcomm; and Srinivas Banna, a fellow for advanced technology architecture at GlobalFoundries. SE: There seems to be some debate in this group about whether we’r... » read more

More Problems Ahead
By Ed Sperling - 14 Aug, 2014 - Comments: 3

Semiconductor Engineering sat down to discuss future scaling problems with Lars Liebmann, a fellow at IBM; Adam Brand, managing director of transistor technology at Applied Materials; Karim Arabi, vice president of engineering at Qualcomm; and Srinivas Banna, a fellow for advanced technology architecture at GlobalFoundries. SE: We’re starting to hear talk about octuple patterning. We’ve ... » read more

What Is A Technology Node, Anyway?
By Katherine Derbyshire - 17 Jul, 2014 - Comments: 0

The idea of clearly defined “technology nodes” has been more theoretical than practical for quite some time now. Electrostatic and power consumption considerations have long made it difficult to scale transistor dimensions at the same rate as memory density. Meanwhile, lithography has become more and more challenging, particularly for the arbitrary patterns commonly seen in logic design. ... » read more

Will 7nm And 5nm Really Happen?
By Mark LaPedus - 14 Jul, 2014 - Comments: 2

Today’s silicon-based finFETs could run out of steam at 10nm. If or when chipmakers move beyond 10nm, IC vendors will require a new transistor architecture. III-V finFETs, gate-all-around FETs, quantum well finFETs, SOI finFETs and vertical nanowires are just a few of the future transistor candidates at 7nm and 5nm. Technically, it’s possible to manufacture the transistor portions of the... » read more

Without Moore’s Law: EDA
By Brian Bailey - 26 Jun, 2014 - Comments: 3

Semiconductor Engineering is examining the assertion about the end of Moore’s Law in a number of different ways. The special report, “Will 7nm and 5nm really happen?” looked at the technical aspects related to continuing into finer geometries. “Moore’s Law Tail No Longer Wagging the Dog” asked the question about the economics of people being able to afford to go to the latest node. ... » read more

Will 7nm And 5nm Really Happen?
By Mark LaPedus - 19 Jun, 2014 - Comments: 11

As leading-edge chipmakers continue to ramp up their 28nm and 20nm devices, vendors are also updating their future technology roadmaps. In fact, IC makers are talking about their new shipment schedules for 10nm. And GlobalFoundries, Intel, Samsung and TSMC are narrowing down the options for 7nm, 5nm and beyond. There is a high probability that IC makers can scale to 10nm, but vendors face a ... » read more

Atomic Layer Etch Finally Emerges
By Mark LaPedus - 15 May, 2014 - Comments: 1

The migration towards finFETs and other devices at the 20nm node and beyond will require a new array of chip-manufacturing technologies. Multiple patterning, hybrid metrology and newfangled interconnect schemes are just a few of the technologies required for future scaling. In addition, the industry also will require new techniques that can process structures at the atomic level. For example... » read more

Gaps In Metrology Could Impact Yield
By Mark LaPedus - 17 Apr, 2014 - Comments: 0

For some time, chipmakers have been developing new and complex chip architectures, such as 3D NAND, finFETs and stacked die. But manufacturing these types of chips is no simple task. It requires a robust fab flow to enable new IC designs with good yields. In fact, yield is becoming a more critical part of the flow. Yield is a broad term that means different things to different parts of the ... » read more

Directed Self-Assembly Gains Momentum
By Mark LaPedus - 20 Mar, 2014 - Comments: 0

At last year’s SPIE Advanced Lithography symposium, directed self-assembly (DSA) grabbed the spotlight as chipmakers provided the first glimpse of their initial work and results with the technology. The results were stunning, thereby propelling DSA from a curiosity item to a possible patterning solution for next-generation devices. Last year, in fact, GlobalFoundries, IBM, Intel and Sams... » read more

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